MIL-M-38510-56 Microcircuits, Digital, Cmos, Counters/Dividers, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/56G

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 1/ VSS = 0 V, -55°C ≤ TC ≤ 125°C unless otherwise specified				Device type	Limits		Unit
Test	Symbol					Device type	Min	Max	Unit
Propagation delay time, low-to-high level, high-to-low level	tPLH, tPHL	VDD = 5.0 V, CLOCK to			Q1	55	.013	0.49	µs
					Q2		.026	0.77
					Q3		.039	1.05
					Q4		.052	1.33
					Q5		.055	1.61
					Q6		.078	1.89
					Q7		.097	2.17
Transition time, high- to-low level = transition time, low-to-high level	tTHL, tTLH	VDD = 5.0 V	CARRY output			01	10	825	ns
	tTHL, tTLH	VDD = 5.0 V	DECODED outputs			01	.010	3.38	µs
	tTHL	VDD = 5.0 V, CARRY and DECODED outputs				51,54	10	280	ns
	tTLH	VDD = 5.0 V, CARRY and DECODED outputs				51,54	10	504	ns
	tTHL, tTLH	VDD = 5.0 V		Q5 output		02	10	825	ns
				Q1 - Q4 outputs		02	.010	3.38	µs
				Q1 - Q5 outputs		52	10	350	ns
		VDD = 5.0 V, all outputs				03	.010	1.73	µs
		VDD = 5.0 V, all outputs				53	10	280	ns
	tTHL	VDD = 5.0 V, CARRY output and DECODED outputs				04	"	750	ns
	tTLH	VDD = 5.0 V, CARRY output and DECODED outputs				04	"	900	ns
	tTHL	VDD = 5.0 V, all outputs				05	"	645	ns
	tTHL	VDD = 5.0 V, all outputs				55	"	280	ns
	tTLH	VDD = 5.0 V, all outputs				05	"	1050	ns
	tTLH	VDD = 5.0 V, all outputs				55	"	280	ns
Minimum setup time, high-to-low level	tSHL	VDD = 5.0 V, CLOCK input to RESET or CLOCK enable (DECODED outputs)				01		1125	ns
		VDD = 5.0 V, CLOCK input to CLOCK ENABLE (CARRY, DECODED outputs)				51		336	ns
		VDD = 5.0 V, CLOCK input to RESET or CLOCK ENABLE (CARRY output)				01		750	ns
		VDD = 5.0 V, CLOCK input to RESET				51		560	ns
		VDD = 5.0 V, CLOCK input to RESET or PRESET ENABLE				02		1125	ns
		VDD = 5.0 V, CLOCK input to RESET or PRESET ENABLE				52		560	ns
		VDD = 5.0 V, CLOCK input to data line				02		750	ns
		VDD = 5.0 V, CLOCK input to data line				52		280	ns
Minimum set-up time, low-to-high level	tSLH	VDD = 5.0 V, CLOCK input to data line				02		750	ns
Minimum set-up time, low-to-high level	tSLH	VDD = 5.0 V, CLOCK input to data line				52		280	ns
Minimum set-up time, high-to-low level	tSHL	VDD = 5.0 V, CLOCK input to CLOCK ENABLE or RESET				04		1125	ns
		VDD = 5.0 V, CLOCK input to CLOCK ENABLE				54		350	ns
		VDD = 5.0 V, CLOCK input to RESET				54		560	ns
Minimum clock pulse width	tPH	VDD = 5.0 V VIH = 5.0 V				01,02,04		750	ns
						51		350
						52		700
						54		550

See footnotes at end of table.