TABLE III. Group A inspection for device type 01, 03, 05, and 07 - Continued. Terminal conditions (pins not designated may be high 2.0 V; or low σ 0.8 V; or open).
0 1 2
3 4 5
OUT SS
IN 11 10 9 8 7
6 CC
1/ See appendix for description of algorithms.
2/ ICC = 160 for device type 01; 180 for device types 03, 05 and 07.
3/ VIL = GND, VIH = 6.0 V, pause time = 250 ms/loop max, CS = high, only performed once at 125°C, and VCC = 0.7 V min.
4/ VIL = 0.8 V and VIH = 2.0 V.
5/ Algorithm has 60 ms where chip is deselected between the write.
6/ VIL = GND, VIH = 3.0 V, and all address setup times are shown at minimum.
7/ VIL = GND, VIH = 3.0 V and all write pulse timing are at a minimum.
8/ VIL = GND, VIH = 3.0 V and all address ending timing are at minimums.
9/ VIL = GND, VIH = 3.0 V, and tAA is measured at minimum timing.
10/ VIL = GND, VIH = 3.0 V, tACS1 and tACS2 are measured at minimum timing.
11/ VIL = 0.8 V, VIH = 2.0 V, and all parameters are measured at minimum timing.
12/ tAA = 85 ns for device type 01; 70 ns for device type 03; 55 ns for device type 05; 45 ns for device type 07.
13/ tACS1 = 85 ns for device type 01; 70 ns for device type 03; 55 ns for device type 05; 45 ns for device type 07.
14/ tACS2 = 100 ns for device type 01; 80 ns for device type 03; 65 ns for device type 05; 555 ns for device type 07.
15/ tWC = 85 ns for device type 01; 70 ns for device type 03; 55 ns for device type 05; 45 ns for device type 07.
16/ tCW = 70 ns for device type 01; 55 ns for device type 03; 45 ns for device types 05 and 07.
17/ tAW = 70 ns for device type 01; 55 ns for device type 03; 45 ns for device types 05 and 07.
18/ tWP = 55 ns for device type 01; 40 ns for device type 03; 25 ns for device type 05; 25 ns for device type 07.
19/ tWR = 15 ns for device type 01 and 03; 10 ns for device type 05 and 07.
20/ tDW = 35 ns for device type 01; 30 ns for device type 03; 25 ns for device type 05; 25 ns for device type 07.
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