MIL-M-385101238B
TABLE I. Electrical performance characteristics - Continued.
Test |
Symbol |
Conditions -55°C < TC < +125°C unless otherwise specified |
Device types |
Limits |
Unit |
|
Min |
Max |
|||||
Write recovery time |
tWR |
See table III |
01, 03 |
15 |
ns |
|
02, 04 |
0 |
ns |
||||
05, 07 |
10 |
ns |
||||
06 |
5 |
ns |
||||
Data valid to end of write |
tDW |
01 |
35 |
ns |
||
02 |
200 |
ns |
||||
03 |
30 |
ns |
||||
04 |
135 |
ns |
||||
05, 06 |
25 |
ns |
||||
07 |
25 |
ns |
||||
Data hold time |
tDH |
01, 03 05, 07 |
10 |
ns |
||
02, 04, 06 |
0 |
ns |
||||
Write enabled to output in High-Z 41 71 |
tWZ |
01 |
0 |
65 |
ns |
|
02 |
0 |
100 |
ns |
|||
03 |
0 |
35 |
ns |
|||
04 |
0 |
60 |
ns |
|||
05, 06, 07 |
0 |
25 |
ns |
|||
Output active from end of write 41 71 |
tOW |
01, 03, 05, 06, 07 |
0 |
ns |
11 Output levels are tested in static state and are specified over voltage range of VCC.
21 Unless otherwise specified, the dynamic load shall be in accordance with figure 4 (load A).
31 Duration not exceed 1 second.
41 Not tested.
51 Complete terminal conditions are as specified in table III.
61 Chip deselected for a finite time that is less than 55 ns prior to selection. (If the deselect time is 0 ns, the chip is by definition selected and access occurs according to read cycle no 1.)
71 Transition is measured ±500 mV from steady state voltage using figure 4 (load B).
10
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