MIL-M-38510-238 Microcircuits, Digital, Mos, 4096 Bit Static Random Access Memory Ram, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, N-channel static MOS, 4096 bit random access memories. Two product assurance classes and a choice of case outlines/lead finish are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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MIL-M-38510/2388

TA8LE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions -55°C < TC < +125°C unless otherwise specified	Device types	Limits		Unit
Test	Symbol	Conditions -55°C < TC < +125°C unless otherwise specified	Device types	Min	Max	Unit
Chip select access time 6/	tACS2	See table III	01		100	ns
			03		80	ns
			05		65	ns
			06		80	ns
			07		55	ns
Chip select to output in Low-Z 4/ 7/	tLZ		01, 03, 04, 05, 07	10		ns
Chip select to output in Low-Z 4/ 7/	tLZ		02, 06	20		ns
Chip deselect to output in High-Z 4/ 7/	tHZ		01, 03	0	40	ns
			02	0	100	ns
			04	0	60	ns
			05, 07	0	30	ns
			06	0	20	ns
Output hold from address change 4/	tOH		01, 03, 05, 06, 07	5		ns
			02	50		ns
			04	15		ns
Chip select to power up time 4/	tPU		01, 03, 05, 06, 07	0		ns
Chip deselect to power down time 4/	tPD		01, 06		30	ns
Chip deselect to power down time 4/	tPD		03, 05, 07		20	ns
Write cycle time	tWC		01	85		ns
			02	450		ns
			03	70		ns
			04	250		ns
			05	55		ns
			06	70		ns
			07	45		ns
Chip select to end of write	tCW		01	70		ns
			03	55		ns
			05, 07	45		ns
			06	65		ns
Address valid to end of write	tAW		01	70		ns
			03	55		ns
			05, 07	45		ns
			06	65		ns
Address setup time	tAS		01, 03, 05, 06, 07	0		ns
Write pulse width	tWP		01	55		ns
			02	200		ns
			03	40		ns
			04	135		ns
			05	25		ns
			06	50		ns
			07	25		ns