MIL-M-38510-238 Microcircuits, Digital, Mos, 4096 Bit Static Random Access Memory Ram, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, N-channel static MOS, 4096 bit random access memories. Two product assurance classes and a choice of case outlines/lead finish are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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MIL-M-38510/2388

1.4 Recommended operating conditions - Continued.

Device types 03 - Continued Min Max Units

Data valid to end of write (tDW) .......................................................... 30 ns Address set-up time (tAS)................................................................... 0 ns Write recovery time (tWR)................................................................... 15 ns Data on hold time (tDH) ..................................................................... 10 ns

Device type 04

Read cycle time (tRC)......................................................................... 250		ns
Address access time (tAA)..................................................................	250	ns
Chip select access time (tACS) ...........................................................	85	ns
Output hold time from address change (tOH) ..................................... 15		ns
Chip select to output in low-Z (tLZ) 6/ 7/........................................... 10		ns

Chip deselect to output in high-Z (tHZ) 6/ 7/ ...................................... 0 60 ns

Write cycle time (tWC) ....................................................................... 250 ns

Pulse width, write (tWP)...................................................................... 135		ns
Data valid to end of write (tDW) .......................................................... 135		ns
Write recovery time (tWR)................................................................... 0		ns
Data on hold time (tDH) ...................................................................... 0		ns
Write enabled to output in high-Z (tWZ) 7 .......................................... 0	60	ns

Device type 05

Read cycle time (tRC)......................................................................... 55

Address access time (tAA)..................................................................

ns ns

Chip select access time (tACS1) 8/.....................................................

Chip select access time (tACS2) 5/..................................................... Output hold time from address change (tOH) ..................................... 5

Chip select to output in low-Z (tLZ) 6/ 7/............................................ 10

ns ns

Chip deselect to output in high-Z (tHZ) 6/ 7/ ..................................... 0

Chip select to power-up time (tPU)...................................................... 0

Ship select to power-down time (tPD).................................................

ns ns

Write cycle time (tWC)......................................................................... 55

Pulse width, chip select to end of write (tCW) ..................................... 45

Address valid to end of write (tAW)..................................................... 45

Pulse width, write (tWP)...................................................................... 25

Data valid to end of write (tDW) .......................................................... 25

Address set-up time (tAS)................................................................... 0

Write recovery time (tWR)................................................................... 10

Data on hold time (tDH) ...................................................................... 10

Write enabled to output in high-Z (twz) 7/.......................................... 0

ns ns ns ns ns ns ns ns

Output active from end of write (tOW) 7/............................................ 0

Device type 06

Read cycle time (tRC)............................................................... 70 Address access time (tAA)..................................................................	70	ns ns
Chip select access time (tACS1) 8/.....................................................	70	ns
Chip select access time (tACS2) 5/.....................................................	80	ns
Output hold time form address change (tOH)........................... 5 Chip select to output in low-Z (tLZ) 6/ 7/................................. 20 Chip deselect to output in high-Z (tHZ) 6/ 7/................................. 0	20	ns ns ns