MIL-M-38510-238 Microcircuits, Digital, Mos, 4096 Bit Static Random Access Memory Ram, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, N-channel static MOS, 4096 bit random access memories. Two product assurance classes and a choice of case outlines/lead finish are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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MIL-M-38510/2388

1.4 Recommended operating conditions - Continued.

Device types 01 - Continued Min Max Units

Chip select to output in low-Z (tLZ) 6/ 7/............................................ 10	ns
Chip deselect to output in high-Z (tHZ) 6/ 7/ ..................................... 0	40	ns
Chip select to power-up time (tPU) ..................................................... 0		ns
Chip select to power-down time (tPD).................................................	30	ns
Write cycle time (tWC)......................................................................... 85		ns
Pulse width, chip select to end of write (tCW) ..................................... 70		ns
Address valid to end of write (AW)...................................................... 70		ns
Pulse width, write (tWP)...................................................................... 55		ns
Data valid to end of write (tDW) .......................................................... 35		ns
Address set-up time (tAS)................................................................... 0		ns
Write recovery time (tWR)................................................................... 15		ns
Data on hold (tDH).............................................................................. 10		ns
Write enabled to output in high-Z (tWZ) 7/ ......................................... 0	65	ns
Output active from end of write (tow) 7/ .............................................. 0		ns

Device type 02

Read cycle time (tRC)......................................................................... 450

Address access time (tAA)..................................................................

450

ns ns

Chip select access time (tACS) ........................................................... Output hold time from address change (tOH) ..................................... 50

Chip select to output in low-Z (tLZ) 6/ 7/............................................ 20

120

ns ns

Chip deselect to output in high-Z (tHZ) 6/ 7/ ...................................... 0

Write cycle time (tWC)......................................................................... 450

Pulse width, write (tWP)...................................................................... 200

Data valid to end of write (tDW)..................................................... 200

Write recovery time (tWR)................................................................... 0

Data on hold time (tDH) ...................................................................... 0

Write enabled to output in high-Z (twz) 7/.......................................... 0

100

ns ns

ns ns ns ns

Device type 03

Read cycle time (tRC)............................................................... 70 Address access time (tAA)..................................................................	70	ns ns
Chip select access time (tACS1) 8/.....................................................	70	ns
Chip select access time (tACS2) 5/.....................................................	80	ns
Output hold time form address change (tOH)........................... 5 Chip select to output in low-Z (tLZ) 6/ 7/................................. 10 Chip deselect to output in high-Z (tHZ) 6/ 7/................................. 0	40	ns ns ns
Chip select to power-up time (tPU)........................................... 0 Chip select to power-down time (tPD) ......................................	30	ns ns
Write cycle time (tWC)............................................................... 70 Pulse width, chip select to end of write (tCW)........................... 55 Address valid to end of write (tAW)........................................... 55 Pulse width, write (tWP) ............................................................ 40		ns ns ns ns

6/ At any given temperature and voltage condition, tHZ maximum is less than tLZ mimimum both for a given device and from device to device.

7/ Transition is measured ±500 mV from steady state voltage with specified loading.

8/ Chip selected for greater than 55 ns prior to selection.