MIL-M-38510-121 Microcircuits, Linear Monolithic And Multichip, Silicon 12 Bit Digital-To-Analog ConvertersThis specification covers the detail requirements for monolithic silicon, bipolar, interface, memory core drivers. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52

Characteristics

Symbol

Conditions   1/ 2/ 3/

-55°C = TA = +125°C

unless otherwise specified

Device type

Limits

Unit

Min

Max

Power supply sensitivity

from VCC  at full scale

(TTL)

+PSS1

VCC  = 5 ±0.5 V,      8/

TA = 25°C,

VCC  = 5 ±0.25 V

01

-0.04

0.04

LSB/%PS

02

-0.15

0.15

VCC  = 5 ±0.5 V,      8/

-55°C = TA = 125°C, VCC  = 5 ±0.25 V

01

-0.07

0.07

02

-0.25

0.25

Power supply sensitivity

from VCC  at full scale

(CMOS)

+PSS2

VCC  = 15 ±1.5 V,      8/

TA = 25°C,

VCC  = 15 ±0.75 V,

VCC  = 15 ±1.5 V, 12 ± 0.6 V

01

-0.04

0.04

LSB/%PS

02

-0.15

0.15

03

-0.04

0.04

VCC  = 15 ±1.5 V,      8/

-55°C = TA = 125°C, VCC  = 15 ±0.75 V,

VCC  = 15 ±1.5 V, 12 ± 0.6 V

01

-0.07

0.07

02

-0.25

0.25

03

-0.08

0.08

Power supply sensitivity

from VEE at full scale

-PSS

VEE = -15 ±1.5 V,      8/

TA = 25°C,

VEE = -15 ±0.75 V,

VEE = -15 ±1.5 V, -12 ± 0.6 V

01

-0.07

0.07

LSB/%PS

02

-0.25

0.25

03,04

-0.1

0.1

VEE = -15 ±1.5 V,      8/

-55°C = TA = 125°C, VEE = -15 ±0.75 V,

VEE = -15 ±1.5 V, -12 ± 0.6 V

01

-0.15

0.15

02

-0.5

0.5

03,04

-0.2

0.2

Bit linearity error

LE

Subgroups 1, 2, and 3

abbrev. codes test.

Subgroups 7 and 8 all codes test.                   5/  9/

01, 02,

03, 04

-0.5

0.5

LSB

Major carry error

(differential linearity)

MCE

The difference between adjacent codes at all major

transitions (i.e. 0111 1111

1111 to 1000 0000 0000).

5/   8/

01, 02,

03, 04

-1.0

+1.0

LSB

Output current settling

time, zero to full-scale

tSLH

All inputs switched

simultaneously.  Measure the time to settle to within ½ LSB

of the final value. TA = 25°C, See figures 3 and 4

01, 02

----

3.0

∝s

03

----

400

ns

04

----

600

Output current settling

time, full-scale to zero

tSHL

All inputs switched

simultaneously.  Measure the time to settle to within ½ LSB

of the final value. TA = 25°C, See figures 3 and 4

01, 02

3.0

∝s

03

400

ns

04

600