TABLE III. Group A inspection for device type 03 - Continued.
Terminal conditions (pins not designated may be H > 2.0 V or L < 0.8 V or open).
Subgroup |
Symbol |
MIL- STD-883 method |
Cases A, B, C, D |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
Meas. terminal |
Test limits |
||
|
Min |
Max |
Unit |
|||||||||||||||||||
Test No. |
SIA |
SIB |
QA |
QB |
QC |
QD |
GND |
CLK |
CLR |
QE |
QF |
QG |
QH |
VCC |
|||||||
10 TC = 125°C " " " " ’‘ ’‘ " " " " " " ’‘ ’‘ |
tPLH2 " " " " " " " |
3003 (Fig 6) " " " " " " |
198 199 200 201 202 203 204 205 |
IN " " " " " " " |
IN " " " " " " " |
OUT |
OUT |
OUT |
OUT |
GND " " " " " " " |
IN " " " " " " " |
4.5 V " " " " " " " |
OUT |
OUT |
OUT |
OUT |
5.0 V " " " " " " " |
QA QB QC QD QE QF QG QH |
10 " " " " " " " |
42 " " " " " " " |
ns " " " " " " " |
tPHL2 " " " " " " " |
" " " " " " " " |
206 207 208 209 210 211 212 213 |
" " " " " " " " |
" " " " " " " " |
OUT |
OUT |
OUT |
OUT |
" " " " " " " " |
" " " " " " " " |
" " " " " " " " |
OUT |
OUT |
OUT |
OUT |
" " " " " " " " |
QA QB QC QD QE QF QG QH |
" " " " " " " " |
52 " " " " " " " |
" " " " " " " " |
|
11 |
Same tests, terminal conditions and limits as for subgroup 10, except TC = -55° C. |
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1/ A = normal clock pulse, except for subgroups 7 and 8 (see 3/).
2/ B = momentary GND, then 4.5 V to clear register prior to test, except for subgroups 7 and 8 (see 3/).
3/ For subgroups 7 and 8, A = VCC and B = GND.
4/ Output voltages shall be either:
(a) H = 2.4 V minimum and L = 0.4 V maximum when using a high speed checker double comparator, or
(b) H � 1.5 V and L < 1.5 V when using a high speed checker single comparator.
5/ The tests in subgroups 7 and 8 shall be performed in the sequence specified.
6/ Only a summary of attributes data is required.
7/ For schematics incorporating 4.5 kn base resistors, the minimum and maximum limits shall be -0.6 and -1.5 mA, respectively.
For schematics incorporating 6 kn base resistors, the minimum and maximum limits shall be -0.4 and -1.3 mA, respectively.
8/ For device type 03, schematic circuits A, D, E and F, the minimum and maximum limits shall be -0.7 and -1.6 mA, respectively.
For schematic circuit B, the minimum and maximum limits shall be -0.8 and -2.6 mA, respectively. For schematic circuit C, the minimum and maximum limits shall be -0.6 and -1.5 mA, respectively.
9/ For device type 03, schematics circuits A, C, D, E and F, the maximum limits shall be 40 µA. For schematic circuit B, the maximum limits shall be 80 µA.
10/ For device type 03, schematics circuits A, C, D, E and F, the maximum limits shall be 100 µA. For schematic circuit B, the maximum limits shall be 200 µA.
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