MIL-M-38510/9E
Device type 06
Positive logic: The registers have two modes of operation: Parallel (broadside) load
Shift (in direction QA toward QD)
Parallel loading is accomplished by applying the four bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered
at the J - K inputs. These inputs permit the first stage to perform as a J - K , D-, or T-type flip-flop as shown in the truth table.
TRUTH TABLE
H = high level, L = low level
NOTES:
1. tn = bit time before clock pulse
2. tn + 1 = bit time after clock pulse
3. QAn = state of QAn at tn.
Figure 2. Truth tables and timing diagrams - Continued.
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