MIL-M-38510/9E
TABLE I. Electrical performance characteristics - Continued.
Test |
Symbol |
Conditions -55qC ≤ TC ≤ +125qC unless otherwise specified |
Device type |
Limits |
||
Maximum clock frequency |
fMAX |
VCC = 5.0 V, CL = 50 pF ±10% RL = 400 n ±5% (See figure 7) |
04 |
14 |
MHz |
|
Propagation delay time, low to high level, load input to any output |
tPLH1 |
10 |
40 |
ns |
||
Propagation delay time, high to low level, load input to any output |
tPHL1 |
11 |
60 |
ns |
||
Propagation delay time, low to high level, clock input to any output |
tPLH2 |
6 |
37 |
ns |
||
Propagation delay time, high to low level, clock input to any output |
tPHL2 |
10 |
47 |
ns |
||
Propagation delay time, low to high level, H input to QH output |
tPLH3 |
5 |
27 |
ns |
||
Propagation delay time, high to low level, H input to QH output |
tPHL3 |
11 |
54 |
ns |
||
Propagation delay time, low to high level, H input to QH output |
tPLH4 |
10 |
41 |
ns |
||
Propagation delay time, high to low level, H input to QH output |
tPHL4 |
10 |
41 |
ns |
||
Maximum clock frequency |
fMAX |
VCC = 5.0 V, CL = 50 pF ±10% RL = 400 n ±5% (See figure 8) |
05 |
18 |
MHz |
|
Propagation delay time, high to low level, output from clear |
tPHL1 |
7 |
48 |
ns |
||
Propagation delay time, low to high level output from clock |
tPLH2 |
7 |
36 |
ns |
||
Propagation delay time, high to low level output from clock |
tPHL2 |
7 |
44 |
ns |
See footnotes at end of table.
8
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