MIL-M-38510/9E
TABLE I. Electrical performance characteristics - Continued.
Test |
Symbol |
Conditions -55qC ≤ TC ≤ +125qC unless otherwise specified |
Device type |
Limits |
||
Supply current |
ICC |
VCC = 5.5 V 2/ |
01 |
72 |
mA |
|
02 |
68 |
|||||
04, 05, 06 |
63 |
|||||
Supply current |
ICC1 |
VCC = 5.5 V, VIN(CLOCK) = 0.4 V 2/ |
03 |
44 |
mA |
|
ICC2 |
VCC = 5.5 V, VIN(CLOCK) = 2.4 V 2/ |
03 |
54 |
mA |
||
Maximum shift frequency |
fMAX |
VCC = 5.0 V, CL = 50 pF ±10% RL = 400 n ±5% (See figure 4) |
01 |
16 |
MHz |
|
Propagation delay time, low to high level from clock 1 or clock 2 to outputs |
tPLH |
10 |
42 |
ns |
||
Propagation delay time, high to low level from clock 1 or clock 2 to outputs |
tPHL |
10 |
49 |
ns |
||
Maximum clock frequency |
fMAX |
VCC = 5.0 V, CL = 50 pF ±10% RL = 400 n ±5% (See figure 5) |
02 |
7 |
MHz |
|
Propagation delay time, low to high level from clock to output |
tPLH1 |
8 |
56 |
ns |
||
Propagation delay time, high to low level from clock to output |
tPHL1 |
8 |
56 |
ns |
||
Propagation delay time, low to high level from preset to output |
tPLH2 |
8 |
59 |
ns |
||
Propagation delay time, high to low level from clear to output |
tPHL3 |
8 |
77 |
ns |
||
Maximum clock frequency |
fMAX |
VCC = 5.0 V, CL = 50 pF ±10% RL = 800 n ±5% (See figure 6) |
03 |
18 |
MHz |
|
Propagation delay time, high to low level, clear input to Q outputs |
tPHL1 |
12 |
63 |
ns |
||
Propagation delay time, high to low level, clock input to Q outputs |
tPHL2 |
10 |
52 |
ns |
||
Propagation delay time, low to high level, clock input to Q outputs |
tPLH2 |
10 |
42 |
ns |
||
See footnotes at end of table.
7
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