MIL-M-38510-71 Microcircuits, Digital, Bipolar, Schottky Ttl, Flip-Flops, Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, Schottky TTL, bistable logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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Subgroup

Symbol

MIL- STD-883 method

Cases A, B,C,D

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Measured terminal

Test limits

Unit

Test no.

CLR

K1

J1

PRE 1

Q1

Q1

GND

Q2

Q2

PRE 2

J2

K2

CLK

VCC

Min

Max

7  3/  4/

TC = +25°C

90

91

92

93

94

95

96

97

A "

" " " " " "

A " B "

"

A "

"

A " B "

"

A "

"

A " " " " " " "

L H "

" " " "

L

H L "

" " " "

H

GND "

" " " " " "

H L "

" " " "

H

L H "

" " " "

L

A "

" " " " " "

A " B "

"

A "

"

A " B "

"

A "

"

A B B A B B A B

4.5 V "

" " " " " "

All outputs "

" " " " "

H or L  5/ as shown "

" " " " "

V "

" " " " " "

8  3/  4/

Same tests, terminal conditions and limits as for subgroup 7, except TC = +125°C and -55°C.

9

TC = +25°C

fMAX

6/

Fig. 7 "

" "

98

99

100

101

2.7 V "

" "

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

OUT

OUT

GND "

" "

OUT

OUT

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

IN (A) "

" "

5.0 V "

" "

Q1

Q2

Q1

Q2

80 "

" "

MHz

" " "

tPLH1

" " " "

102

103

104

105

IN (B) IN (B) IN (C) IN (C)

2.7 V

2.7 V

2.7 V

2.7 V

IN (C) IN (B)

OUT

OUT

" " " "

OUT

OUT

IN (C) IN (B)

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V "

" "

" " " "

PRE 1 to Q1

PRE 2 to Q2

CLR to  Q1

CLR to  Q2

2.0 "

" "

9.0 "

" "

ns

" " "

tPLH2

Fig. 8 "

" "

106

107

108

109

E E

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V E

OUT

OUT

" " " "

OUT

OUT

2.7 V E

2.7 V

2.7 V

2.7 V

2.7 V

IN (A) "

" "

" " " "

CLK to  Q1

CLK to Q2

CLK to Q1

CLK to Q2

" " " "

" " " "

" " " "

tPHL3

Fig. 7 "

" "

110

111

112

113

IN (B) IN (B) IN (C) IN (C)

2.7 V

2.7 V

2.7 V

2.7 V

IN (C) IN (B)

OUT

OUT

" " " "

OUT

OUT

IN (C) IN (B)

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V "

" "

" " " "

PRE 1 to  Q1

PRE 2 to Q2

CLR to Q1

CLR to Q2

" " " "

" " " "

" " " "

tPHL2

Fig. 8 "

" "

114

115

116

117

E E

2.7 V "

2.7 V

2.7 V

2.7 V

2.7 V

2.7 V E

OUT

OUT

" " " "

OUT

OUT

2.7 V E

2.7 V

2.7 V

2.7 V

2.7 V

IN (A) "

" "

" " " "

CLK to  Q1

CLK to Q2

CLK to Q1

CLK to Q2

" " " "

" " " "

" " " "

tSETUP

(L)

Fig. 9 "

" "

118

119

120

121

" " E

E

GND IN (D)

IN (D) GND

E

2.7 V

OUT

OUT

" " "

"

OUT

OUT

E

2.7 V

IN (D)

GND

GND

IN (D)

" " "

"

" " "

"

Q1

Q2

Q1

Q2

7/ "

" "