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MIL-M-38510-71 Microcircuits, Digital, Bipolar, Schottky Ttl, Flip-Flops, Cascadable, Monolithic SiliconThis specification covers the detail requirements for monolithic, silicon, Schottky TTL, bistable logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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TABLE III. Group A inspection for device type 01 - Continued.

Terminal conditions (pins not designated may be high > 2.0 V, low < 0.8 V, or open).

Subgroup

Symbol

MIL- STD-883 method

Cases X, 2 1/

Measured terminal

Test limits

Unit

Cases A, B,C,D

Test no.

CLR 1

CLK 1

PRE 1

GND

PRE 2

CLK 2

CLR 2

VCC

Min

Max

TC = +125°C

fMAX

Fig. 5

124, 145

Same tests and terminal conditions as subgroup 9, except TC = +125°C and limits are as shown.

MHz

tPLH1

Fig. 4

126-129

2.0

10.0

tPLH2

Fig. 5 8/

130-133

16.0

tPHL2

Fig. 5 8/

134-137

13.0

tPHL3

Fig. 5

138-141

19.0

tPHL4

Fig. 4

142-145

12.5

tSETUP (H)

Fig. 5

146-149

tSETUP (L)

150-153

t(HOLD) (H)

154-157

t(HOLD) (L)

158-161

Same tests, terminal conditions, and limits as for subgroup 10, except TC = -55°C.

1/ Cases X and 2 terminals not designated are NC.

2/ C = Normal clock pulse.

D = Momentary connection: 5.0 V to GND to 5.0 V (for subgroup 9, 10, 11. D occurs prior to their input pulses). E = Data input connected to Q output.

F = Normal input conditioning is 5.0 V, however, momentary logic "0" may be applied for synchronizing test equipment for preconditioning the device.

3/ For circuit B, IOS(max) is -110 mA.

4/ Only a summary of attributes data is required.

5/ Inputs: A = 2.4 V minimum, B = 0.4 V.

6/ Outputs: H � 1.5 V, L ≤ 1.5 V.

7/ fMAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency.

8/ SETUP and HOLD time functionality may be verified by separate tests from propagation delay tests, by monitoring the output at

specified SETUP and HOLD conditions (see fig. 5).