MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33

MIL-M-38510/502A APPENDIX A

GATE TEST PROGRAM AND FUNCTIONAL TESTS

A.1  SCOPE

A.1.1  This Appendix A covers the fuse test program to be used for unprogrammed devices, and defines the requirements for functional tests of unprogrammed devices.  This Appendix is a mandatory part of this standard.  The information contained herein is intended for compliance.

A.2  GATE TEST PROGRAM.

A.2.1 When required, as in paragraph 3.3.2.1, the device may be programmed as shown in table A-I.  This program will allow for testing all of the available gates.

A.3  FUSE TESTS FOR DEVICE TYPES 01 AND 02.

A.3.1  Unprogrammed devices - Circuit A. A.3.1.1  Output polarity fuse check.

Terminal conditions:                        VCC  = 8.5 V FE  = 1.5 V CE  = GND

All inputs = 3.0 V

a.    Sense all outputs for logic low, any high is a failure. A.3.1.2  "AND" matrix fuse check.

Terminal condition:                          VCC  = 4.5 V FE  = 1.5 V CE  = 10 V

All inputs = 10 V (except for input being checked)

a.    Address all "P" terms with a binary count 0-47, put into F0  to F5  with F0  = LSB and F5  =MSB.

b.    Sense output F7  for each "P" term.  F7 should also be low and if it goes high, then it means a failure

since a fuse is open.  The input being checked should be set first to VIH  and then VIL.  F7 should

remain low in both cases.

c.    Repeat b for all inputs, one at a time.

d.    Repeat a and then b for all "P" terms and their inputs. A.3.1.3  "OR" (Sum) matrix fuse check.

Terminal condition:                          VCC  = 8.5 V FE  = 1.5 V

I6  - I15 = Open

I0  - I15 = Binary Count Input for address

CE  = GND

a.    Sense each output for logic high.  Any low is a failure, indicating a fuse open. b.    Sense all output low when binary input count goes to 48.  Any high is a failure.

28