MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-38510/502A

4.7.2      Program summing matrix.

4.7.2.1   All 8 OR gates of the summing matrix are fuse linked to the outputs of the AND gates in the initial unprogrammed state.  The initial logic expressions (sum of products) of the eight unprogrammed OR gates is P0 + P1 + P2 + 0 0 0 + P47 where Pm is the product term programmed into the mth AND gate. Programming the fuse located by the selection of the mth AND gate and the nth summing line replaces the

product term Pm with '0' in the logic expression of the nth OR gate.  The nth summing line is selected by the selection of the nth output buffer where n = 1 through 8.

a.    Connect pin 28 (VCC) to 5.0 V.

b.    Connect pin 14 (GND) to ground.

c.    Connect pin 19 ( CE ) to a TTL HIGH level.

d.        Apply TTL levels to pins 4 through 9 (I5  through I0) to address an on chip one of forty-eight decoder to select the AND gate to be programmed (I0  = LSB and I5  = MSB).

e.    Apply a TTL HIGH level to pins 20 and 21 (I15  and I14). f.     Connect the remaining input pins to 12.0 V.

g.        Apply an 18 V programming pulse (see programming specification table) at the pin of the output to be programmed.  Other output pins should be either left open or tied to a TTL HIGH level.

h.    Progran one output pin at a time.

i.     All unused product lines are not required to be programmed.

4.7.2.2   Verify summing matrix.

a.    Connect pin 28 (VCC) to 5.0 V.

b.    Connect pin 14 (GND) to ground.

c.    Connect pin 19 ( CE ) to a TTL LOW level.

d.        Apply TTL levels to pins 4 through 9 (I5  through I0) to address an on chip one of forty eight decoder to select the AND gate to be verified (I0  = LSB and I5  = MSB).

e.        Apply a TTL HIGH level to pins 20 and 22 (I15  and I13). f.     Connect the remaining input pins to 12.0 V.

g.        Sense the voltage on the output pin to be verified.  The programming of the selected product line to the output line can be determined as follows:

h.    Repeat steps d through g with VCC  at 4.4 V (LOW VCC  read).

i.     The condition of the fuse link can be determined from the table above regardless of the polarity (active

HIGH or active LOW) of the output buffer being verified.

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