MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-38510/502A

4.7.3 Program output polarity.

4.7.3.1 The initial unprogrammed state of all eight output buffers is active LOW or inverting. To program an output buffer into the active HIGH or non-inverting state, proceed as follows:

a. Connect pin 28 (VCC) to 5.0 V.

b. Connect pin 14 (GND) to ground.

c. Connect pin 19 ( CE ) to a TTL HIGH level.

d. Apply a TTL HIGH level to pins 4 through 9 (I5 through I0). e. Apply a TTL HIGH level to pin 20 (I15).

f. Connect the remaining input pins to 12.0 V.

g. Apply an 18 V programming pulse (see programming specifications table) to the pin of the output to be programmed. Other output pins should be either left open or tied to a TTL HIGH level.

h. Program one output at a time.

4.7.3.2 Verify output polarity.

a. b.	Connect pin 28 (VCC) to 5.0 V. Connect pin 14 (GND) to ground.
c.	Connect pin 19 ( CE ) to a TTL LOW level.
d.	Apply a TTL HIGH level to pins 4 through 9 (I5 through I0).
e.	Apply a TTL HIGH level to pins 21 and 22 (I14 and I13).
f.	Connect the remaining input pins to 12.0 V.
g.	Sense the voltage on the pin of the output buffer to be verified. determined as follows:	The condition of the output can be

Output reads	Output state
H	Active LOW
L	Active HIGH

h. Repeat with VCC at 4.4 V (LOW VCC read).

4.7.4 Summary of pin voltage - circuit B. In addition to verifying the Product (AND) Matrix, Summing Matrix, and Output Polarity separately after programming, a complete logic verification (normal read) with VCC at 5.0 V is recommended after a device has been fully programmed. Table VI summarizes the full programming and verifying procedures.