MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-3851O/5O2A

f.        For class S and B devices, if any output polarity does not verify as programmed, it shall be considered a programming reject.  For class C devices, if any output does not verify as programmed, repeat 4.6.1.1 one time only.  Outputs which fail to program the second time shall be considered programming rejects.

4.6.2       "AND" Matrix.

4.6.2.1   Programming input variable.  Program one input at a time and one P-term at a time.  All input variable links of unused P-terms are not required to be fused.  However, unused input variables must be programmed as Don't Care for all programmed P-terms.

a.    Set GND (pin 14) to O V, and VCC  (pin 28) to VCCP.

b.    Disable all device outputs by setting  CE  (pin 19) to VIH.

c.    Disable all input variables by applying VIX to inputs IO  through I15.

d.        Address the P-term to be programmed (No. O through 47) by forcing the corresponding binary code on outputs FO  through F5  with FO as LSE.  Use standard TTL logic levels VOHF  and VOLF.

e.        If the P-term contains neither IO  or   I  O  (input is a Don't care), fuse both IO and   I  O  links by executing both steps f and g, before continuing with step k.

f.     If the P-term contains IO, set to fuse the   I  O  link by lowering the input voltage at IO from VIX to VIL.

Execute steps h, i, and j.

g.    If the P-term contains   I  O, set to fuse the IO  link by lowering the input voltage at IO from VIX to VIL.

Execute steps h, i, and j.

h.    After tD  delay, raise FE (pin 1) from VFEL to VFEH.

i.     After tD  delay, pulse the  CE  input from VIH  to VIX for a period of tP. j.     After tD  delay, return FE input to VFEL.

k.    Disable programmed input by returning IO  to VIX.

l.     Repeat steps e through k for all other input variables. m.   Repeat steps d through e for all other P-terms.

n.    Remove VIX from all input variables.

4.6.2.2   Verify input variable.

a.    Set GND (pin 14) to O V, VCC  (pin28) to VCCP, and FE (pin 1) to VFEL. b.    Enable F7  output by setting CE to VIX.

c.    Disable all input variables by applying VIX to inputs IO  through I15.

d.        Address the P-term to be verified (No. O through 47) by forcing the corresponding binary code on outputs FO  through F5.

e.    Interrogate input variable IO  as follows:

1.    Lower the input voltage to IO  from VIX to VIH, and sense the logic state of output F7.

2.    Lower the input voltage to IO  from VIH  to VIL, and sense the logic state of output F7.

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