MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-38510/502A

TABLE IV. Programming characteristics - Circuit A. 4/

Symbol	Parameter	Test Conditions	Limits			Unit
Symbol	Parameter	Test Conditions	Min	Type	Max	Unit
VCCS 1/ 2/	VCC supply (program/verify "OR" verify output program)	ICCS = 550 mA, min (Transient or steady state)	8.25	8.5	8.75	V
VCCL	VCC supply (Program output polarity)		0.	0.4	0.8	V
ICCS	ICC limit (Program "OR")	VCCS = + 8.50 ± .25 V	550		1000.	mA
VOPH 2/	Output voltage (Program output polarity)	IOPH = 300 ± 25 mA	16.0	17.0	18.0	V
VOP1	Output voltage (Idle)	IOPH = 300 ± 25 mA	0.	0.4	0.8	V
IOPH	Output current limit (Program output polarity)	VOPH = +17 ± 1.0 V	275	300	325	mA
VIH	Input voltage (Logic "1")		2.4		5.5	V
VIL	Input voltage (Logic "0")		0.	0.4	0.8	V
IIH	Input current (Logic "1")	VIH = +5.5 V			50	µA
IIL	Input current (Logic "0")	VIL = 0 V			-500	µA
VOHF	Forced output (Logic "1")		2.4		5.5	V
VOLF	Forced output (Logic "0")		0.	0.4	0.8	V
IOHF	Output current (Logic "1")	VOHF = +5.5 V			100	µA
IOLF	Output current (Logic "0")	VOLF = 0 V			-1	mA
VIX	CE program enable level		9.5	10	10.5	V
IIX1	Input variables current	VIX = +10 V			2.5	mA
IIX2	CE input current	VIX = +10 V			5.0	mA
VFEH 2/	FE supply (Program)	IFEH = 300 ± 25 mA (Transient or steady state)	16.0	17.0	18.0	V
VFEL	FE supply (Idle)		1.25	1.5	1.75	V
IFEH	FE supply current limit	VFEH = + 17 ± 1.0 V	275	300	325	mA
VCCP 1/	VCC supply (Program "AND")	ICCP = 550 mA, min (Transient or steady state)	4.75	5.0	5.25	V
ICCP	ICC limit (Program "AND")	VCCP = + 5.0 ± .25 V	550		1000	mA
VOPF	Forced output (Program)		9.5	10	10.5	V
IOPF	Output current (Program)				10	mA
TR	Output pulse rise time		10		50	µs
tP	CE programming pulse width		1		1.5	ms
tD	Pulse sequence delay		10			µs
TPR	Programming time			.6		ms
TPR TPR + TPS	Programming duty cycle				50	%
FL	Fusing attempts per link				2	cycle
VS 3/	Verify threshold		1.4	1.5	1.6	V

1/ Bypass VCC to GND with a 0.01 µf capacitor to reduce voltage spikes.

2/ Care should be taken to ensure that the voltage is maintained during the entire fusing cycle. The recommended supply is a constant current source clamped at the specified voltage limit.

3/ VS is the sensing threshold of the FPLA output voltage for a programmed link. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt.

4/ These are specifications which a programming system must satisfy.

5/ TC = 25 ° C.