MIL-M-38510/502A
f. The state of I0 contained in the P-term is determined in accordance with the following truth table:
I0 |
F7 |
Input variable state contained in P-term 1/ |
0 |
1 |
I 0 |
1 |
0 |
|
0 |
0 |
I0 |
1 |
1 |
|
0 |
1 |
Don't Care |
1 |
1 |
|
0 |
0 |
(I0), ( I 0 ) |
1 |
0 |
1/ Two tests are required to uniquely determine the state of the input variable contained in the P-term.
g. Disable verified input by returning to I0 to VIX.
h. Repeat steps e and g for all other input variables. i. Repeat steps d through h for all other P-terms.
j. Remove VIX from all input variables.
k. For class S and B devices, if any gate does not verify as programmed, it shall be considered a programming reject.
4.6.3 "OR" (Sum) Matrix.
4.6.3.1 Program product term. Program one output at a time for a P-term at the time. All Pn links in the "OR" matrix corresponding to unused outputs and unused P-terms are not required to be fused.
a. Set GND (pin 14) to 0 V, and VCC (pin 28) to VCCS. b. Disable the chip by setting CE (pin 19) to VIH.
c. Set inputs I6 through I15 to VIH or VIL.
d. Address the P-term to be programmed (No. 0 through 47) by applying the corresponding binary code to input variables I0 through I5, with I0 as LSB.
e. If the P-term is contained in output functions F0 (F0 = 1 or F0 = 0), go to step g, (fusing cycle not required).
f. If the P-term is not contained in output function F0 (F0 = 0 or F0 = 1), set to fuse the Pn link by forcing output F0 to VOPF.
g. After tD delay, raise FE (pin 1) from VFEL to VFEH.
h. After tD delay, pulse the CE input from VIH to VIX for a period tP. i. After tD delay, return FE input to VFEL.
j. After tD delay, remove VOPF from output F0.
k. Repeat steps e through j for all other output functions. l. Repeat steps d through k for all other P-terms.
m. Remove VCCS from VCC.
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