MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-38510/502A

b. Electrical parameters shall be as specified in table II herein.

4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows:

a. End-point electrical parameters shall be as specified in table II herein.

b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883.

c. For qualification, at least 50 percent of the sample selected for life testing shall be programmed (see

3.3.2). For quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the life test.

4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535; end point electrical parameters shall be as specified in table II herein.

4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows:

4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal.

4.6 Programming procedure for circuit A. The programming specifications in table IV and the following procedures shall be used for programming the device.

4.6.1 Output polarity.

4.6.1.1 Program active low (FP function). Program output polarity before programming "AND" matrix and "OR" matrix. Program 1 output at a time. (S) links of unused outputs are not required to be fused.

a. Set GND (pin 14), and FE (pin 1) to 0 V. b. Set VCC (pin 28) to VCCL.

c. Set CE (pin 19), and I0 through I15 to VIH.

d. Apply VOPH to the appropriate output, and remove after a period tp. e. Repeat step D to program other outputs.

4.6.1.2 Verify output polarity.

a. Set GND (pin 14) to 0 V, and VCC (pin 28) to VCCS. b. Enable the chip by setting CE (pin 19) to VIL.

c. Address a non-existent P-term by applying VIH to all inputs I0 through I15.

d. Verify output polarity by sensing the logic state of outputs F0 through F7. All outputs at a high logic level are programmed active low (FP function), while all outputs at a low logic level are programmed active high (FP function).

e. Return VCC to VCCP or VCCL.