MIL-M-38510-502 Microcircuits, Digital, Bipolar Field Programmable Logic Array Fpla 16 X 48 X 8, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, bipolar, field programmable logic array FPLA microcircuits which employ thin film nichrome resistors WICr as the fusible link or programming element. Three product assurance classes and a choice of case outline/lead material and finish are provided for each type and are reflected in the complete part number.

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MIL-M-38510/502A

h. Repeat steps e through g for each input of the selected product term.

i. Repeat steps d through h for all other product terms to be programmed. j. Program one input at a time.

k. All unused inputs of programmed product terms must be programmed as DON'T CARES. l. Inputs of unused product lines are not required to be programmed.

m. Pin 18 (F0) is in the read mode (open collector). Care must be taken so that this pin is either left open, grounded, or loaded such that the current flowing into the pin does not exceed 16 mA.

4.7.1.2 Verify "PRODUCT (AND)" matrix. a. Connect pin 28 (VCC) to 5.0 V.

b. Connect pin 14 (GND) to ground.

c. Connect pin 19 ( CE ) to a TTL HIGH level.

d. Apply TTL levels to pins 10 through 13, 15, and 16 (F7 through F2) to address an on chip one of forty- eight decoder to select the AND gate to be verified (F7 = LSB and F2 = MSB).

e. Apply 10.8 V to all input pins (I0 through I15). f. Test the state of the Ix input as follows:

1. Lower the Ix pin to a TTL HIGH level and sense the voltage on pin 18 (F0).

2. Lower the Ix pin to a TTL LOW and sense the voltage on pin 18 (F0). g. The state of the Ix input is determined as follows:

	Ix = TTL HIGH	Ix = TTL LOW	Condition of Ix for selected product term.
Level at output F0	H	H	Don't Care
	H	L	Ix IN P-term
	L	H	Ix IN P-term unprogrammed
	L	L	Ix IN P-term unprogrammed

NOTES:

1. F0 in this mode functions as an open collector output, H = � 2.0 V, L s 0.8 V.

2. The table above is valid regardless of the polarity (active HIGH or active LOW) of F0.

3. Pin 1 (FE) should be either floating or grounded.