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MIL-M-38510-175 Microcircuits, Digital, Cmos, Positive Logic, Flip-Flops And Monostable Multivibrator, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE III. Group A inspection for device type 05 - Continued.

Symbol

MIL-

STD-

883 method

Cases

E,F,Z

Terminal conditions 1/

Measured

terminal

Test limits

Units

Subgroup 12

TA = 25°C

Symbol

VSS

CLK

VDD

Test No.

Min

Max

Min

Max

Min

Max

tTHL tTHL tTHL tTLH "

" " " "

3004

Fig. 4 "

" "

214

215

216

217

218

219

220

221

222

10.0V

" " "

" " " "

OUT

GND

GND GND IN2

GND

" " " "

GND

" " "

IN2

GND "

" "

OUT

GND

" " "

IN2

GND GND GND

OUT

GND

" " "

" " " "

IN1

" " "

" " " "

OUT

IN2

GND "

" "

" IN2

GND

OUT

GND

IN2

GND "

" " "

IN2

GND

GND IN2

GND "

" "

IN2

OUT

10.0V

" " "

" " " "

" " "

" " " "

100

" " "

" " " "

∝s

" " " " " " "

1/ Pins not designated may be "high" level logic, "low" level logic or open. Exceptions are as follows: VIC(pos) tests, the VSS terminals shall be open; VIC(neg) tests, the VDD terminal shall be open; ISS tests, the output terminals shall be open.

2/ The ISS measurements shall be performed in sequence.

3/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.

4/ The truth table tests shall be performed in sequence.

5/ The truth table tests shall be performed at VIH and VDD ≤ 5 Vdc and 18 Vdc. "L" = VSS + 0.5 V maximum and "H" = VDD -0.5 V minimum.

6/ See 4.4.1c.

7/ Apply clock pulse VIN = 0 to 18 Vdc.

8/ Apply clock pulse VIN = 0 to 15 Vdc.

9/ Apply clock pulse VIN = 0 to 5 Vdc.

10/ The minimum clock frequency (fCLK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.

11/ The minimum clock, or clear pulse width (tpH(CLK), and tpH(CLR) requirement is considered met if proper output changes occur with the pulse width set to that given in the limits column.

12/ Pulse repetition period = 100 μs, 50 percent duty cycle. The maximum clock transition time (tr(CLK), tf(CLK)) requirement is considered met if proper output state changes occur with rise time set to that given in the limits column.