TABLE III. Group A inspection for device type 01 - Continued.
Symbol |
MIL- STD- 883 method |
Cases E,F,Z |
Terminal conditions 1/ |
Measured terminal |
Test limits |
Unit |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
Subgroup 12 TA = 25°C |
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Symbol |
M |
N |
Q1 |
Q2 |
Q3 |
Q4 |
CLK |
VSS |
G1 |
G2 |
D4 |
D3 |
D2 |
D1 |
R |
VDD |
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Test no. |
Min |
Max |
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tPZH 7/ " " |
Fig. 4 " " " |
339 340 341 342 |
IN2 " " " |
GND " " " |
OUT |
OUT |
OUT |
OUT |
IN1 " " " |
GND " " " |
GND " " " |
GND " " " |
10.0V " " " |
10.0V " " " |
10.0V " " " |
10.0V " " " |
GND " " " |
10.0V " " " |
M to Q1 M to Q2 M to Q3 M to Q4 |
8 " " " |
150 " " " |
ns " " " |
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tPZL 8/ " " |
" " " " |
343 344 345 346 |
GND " " " |
IN2 " " " |
OUT |
OUT |
OUT |
OUT |
" " " " |
" " " " |
" " " " |
" " " " |
GND " " " |
GND " " " |
GND " " " |
GND " " " |
" " " " |
" " " " |
N to Q1 N to Q2 N to Q3 N to Q4 |
" " " " |
" " " " |
" " " " |
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1/ Pins not designated may be "high" level logic, "low" level logic or open. Exceptions are as follows: VIC(pos) tests, the VSS terminals shall be open; VIC(neg) tests, the VDD terminal shall be open, ISS tests, the output terminals shall be open.
2/ The ISS measurements shall be performed in sequence.
3/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.
4/ The truth table tests shall be performed in sequence.
5/ The truth table tests shall be performed at VIH and VDD ≤ 5 Vdc and 18 Vdc. "L" = VSS + 0.5 V maximum and "H" = VDD - 0.5 V minimum.
6/ See 4.4.1c.
7/ Pins 3, 4, 5, and 6 tied to VSS through 1 kν resistors.
8/ Pins 3, 4, 5, and 6 tied to VDD through 1 kν resistors.
9/ The minimum clock frequency (fCLK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.
10/ The minimum clock or reset pulse width (tp(CLK), tp(R)) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column.
11/ Pulse repetition period = 100 μs, 50 percent duty cycle. The maximum clock rise or fall time (tr(CLK), tf(CLK)) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column.
12/ 100 kν resistors shall be connected between pins 2 and 14 to GND.
13/ Apply clock pulse; VIN = 0 to 15 Vdc.
14/ Apply clock pulse; VIN = 1.5 to 3.5 Vdc.
15/ Apply clock pulse; VIN = 3.0 to 7.0 Vdc.
16/ Apply clock pulse; VIN = 4.0 to 11.0 Vdc.
17/ Apply clock pulse; VIN = 0 to 5 Vdc.
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