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MIL-M-38510-175 Microcircuits, Digital, Cmos, Positive Logic, Flip-Flops And Monostable Multivibrator, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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12/ The input/output conditions and timing sequence shall apply:


Input/output conditions

Test

VDD

Input levels

Output levels

1

0

1

0


VIL1

VIH1


5.0V "


3.5V


1.5V

Min

4.5V "

Max

0.5V "

VIL2

VIH2

10.0V "


7.0V

3.0V

9.0V "

1.0V "

VIL3

VIH3

15.0V "


11.0V

4.0V

13.5V "

1.5V "


*

Time slot

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

R

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

0

I

J1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

N

J2

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

p

J3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

u

K3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

T

K2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

0

s

K1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

CLK

0

0

0

1

0

1

0

1

0

0

1

0

1

0

0

1

0

1

0

1

0

1

0

0

1

0

1

0

0

1

0

1

0

1

0

1

s

1

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


O

u

       

T

Q

0     1     1

0

0

1

1

1

0

0

1

1

1

0

0

1

1

1

1

0

0

0

1

1

0

0

0

1

1

0

0

0

0

0

0

0

p

Q

1     0     0

1

1

0

0

0

1

1

0

0

0

1

1

0

0

0

0

1

1

1

0

0

1

1

1

0

0

1

1

1

1

1

1

1

u

T

s


* Tests are to be run in sequence.




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