MIL-M-38510-175 Microcircuits, Digital, Cmos, Positive Logic, Flip-Flops And Monostable Multivibrator, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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Test

Symbol

Conditions

VSS = 0 V

-55°C = TA = +125°C Unless otherwise specified

Device type

Limits

Unit

Min

Max

Transition times,

high to low level and low to high level

tTHL, tTLH

VDD  = 5 V dc, CL  = 50 pF RL  = 200 kO

(See figure 4)

see table III for device  type 04

All

10

280

ns

VDD  = 10 V dc, CL = 50 pF RL  = 200 kO

TA = +25°C,  (See figure 4)

see table III for device  type 04

All

5

100

ns

Three-state output propagation delay times, output high to high impedance

tPHZ

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01

15

420

ns

output low to high impedance

tPLZ

high impedance to output low

tPZL

high impedance to output high

tPZH

Three-state output propagation output high to high impedance

tPHZ

VDD  = 10.0 Vdc, CL  = 50 pF RL  = 200 kO (see figure 4)

01

8

150

ns

output low to high impedance

tPLZ

high impedance to output low

tPZL

high impedance to output high

tPZH

Minimum CLOCK transition times, high to low level and

low to high level

tr(CLK), tf(CLK)

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01, 02,

03, 05

15

∝s

Minimum data setup times, high to low level and

low to high level

tSHL, tSLH

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01

280

ns

02, 03

560

05

120

Minimum data hold times, high to low level and

low to high level

tHHL, tHLH

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

05

85

ns

Minimum pulse width, RESET

tP(R)

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01

170

02, 03

280

Minimum pulse width, SET

tP(S)

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

02

280

Minimum pulse width, CLOCK

tP(CLK)

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01, 05

280

02, 03

200

Minimum pulse width, CLEAR

tP(CLR)

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

05

280

Minimum CLOCK frequency

fCLK

VDD  = 5.0 Vdc, CL = 50 pF RL  = 200 kO (see figure 4)

01

1000

ns

02, 03

1400

05

800