TABLE III. Group A inspection for device type 02 - Continued.
Symbol |
MIL- STD-883 method |
Cases A,C,D,X,Y |
Terminal conditions 1/ |
Measured terminal |
Test limits |
Units |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
Subgroup 9 TA = 25°C |
Subgroup 10 TA = 125°C |
Subgroup 11 TA = -55°C |
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Symbol |
NC |
R |
J1 |
J2 |
J3 |
Q |
VSS |
Q |
K3 |
K2 |
K1 |
CLK |
S |
VDD |
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Test No. |
Min |
Max |
Min |
Max |
Min |
Max |
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tSHL1 " " " " " |
Fig. 4 " " " " " |
130 131 132 133 134 135 |
GND " " " " " |
IN2 5.0V " " " " |
5.0V IN2 5.0V " " " |
5.0V " IN2 5.0V " " |
GND " " " " " |
OUT " " " " " |
5.0V " " IN2 5.0V " |
5.0V " " " IN2 5.0V |
5.0V " " " " IN2 |
IN1 " " " " " |
GND " " " " " |
5.0V " " " " " |
CLK to J1 CLK to J2 CLK to J3 CLK to K3 CLK to K2 CLK to K1 |
400 " " " " " |
560 " " " " " |
400 " " " " " |
ns " " " " " |
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tSLH1 " " " " " |
" " " " " " |
136 137 138 139 140 141 |
" " " " " " |
IN2 5.0V " " " " |
" IN2 5.0V " " " |
" " IN2 5.0V " " |
" " " " " " |
" " " " " " |
" " " IN2 5.0V 5.0V |
" " " " IN2 5.0V |
5.0V " " " " IN2 |
" " " " " " |
" " " " " " |
" " " " " " |
J1 to CLK J2 to CLK J3 to CLK K3 to CLK K2 to CLK K1 to CLK |
" " " " " " |
" " " " " " |
" " " " " " |
" " " " " " |
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Subgroup 12 TA = 25°C |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPHL1 " |
3003 Fig. 4 |
142 143 |
GND " |
10.0V " |
10.0V " |
10.0V " |
OUT |
GND " |
OUT |
10.0V " |
10.0V " |
10.0V " |
IN1 " |
GND " |
10.0V " |
CLK to Q CLK to Q |
13 " |
250 " |
ns " |
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tPLH1 " |
" " |
144 145 |
" " |
" " |
" " |
" " |
OUT |
" " |
OUT |
" " |
" " |
" " |
" " |
" " |
" " |
CLK to Q CLK to Q |
" " |
" " |
" " |
|||||
tPHL2 " |
" " |
146 147 |
IN1 " |
GND " |
GND " |
GND " |
OUT |
" " |
OUT |
GND " |
GND " |
GND " |
GND " |
IN2 IN2 |
" " |
S to Q S to Q |
8 " |
150 " |
" " |
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tPLH2 " |
" " |
148 149 |
" " |
" " |
" " |
" " |
OUT |
" " |
OUT |
" " |
" " |
" " |
" " |
GND " |
" " |
R to Q R to Q |
" " |
" " |
" " |
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tTHL " |
3004 Fig. 4 |
150 151 |
GND " |
10.0V " |
10.0V " |
10.0V " |
OUT |
" " |
OUT |
10.0V " |
10.0V " |
10.0V " |
IN1 " |
" " |
10.0V " |
Q Q |
5 " |
100 " |
" " |
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tTLH " |
" " |
152 153 |
" " |
" " |
" " |
" " |
OUT |
" " |
OUT |
" " |
" " |
" " |
" " |
" " |
" " |
Q Q |
" " |
" " |
" " |
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1/ Pins not designated may be "high" level logic, "low" level logic or open. Exceptions are as follows: VIC(pos) tests, the VSS terminals shall be open; VIC(neg) tests, the VDD terminal shall be open; ISS tests, the output terminals shall be open.
2/ The ISS measurements shall be performed in sequence.
3/ The device manufacturer may, at his option, measure IIL and IIH at 25°C for each individual input or measure all inputs together.
4/ See 4.4.1c.
5/ The truth table tests shall be performed in sequence.
6/ The truth table tests shall be performed at VIH and VDD ≤ 5 Vdc and 18 Vdc. "L" = VSS + 0.5 V maximum and "H" = VDD - 0.5 V minimum.
7/ The minimum clock frequency (fCLK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column.
8/ The minimum clock, reset, or set pulse width (tp(CLK), tp(R), tp(S)) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column.
9/ Pulse repetition period = 100 μs, 50 percent duty cycle. The maximum clock rise or fall time (tr(CLK), tf(CLK)) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column.
10/ Apply clock pulse; VIN = 0 to 15 Vdc.
11/ Apply clock pulse; VIN = 0 to 5 Vdc.
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