TABLE III. Group A inspection for device type 53 - Continued.
Symbol MIL- ST0-
Cases
R, S,
Terminal conditions 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Measured terminal
Test limits
Subgroup 9 Subgroup 10 Subgroup 11
Unit
883
and 2
TC = +25°C
TC = +125°C
TC = -55°C
method Test
no. OE 1Q 10 20 2Q 3Q 30 40 4Q GN0 E 5Q 50 60 6Q 7Q 70 80 8Q VCC
Min Max Min Max Min Max
tPZH 3003
176
IN OUT 4.5V
GN0
4.5V
4.5V OE to 1Q 5 31 5
41 5
31 ns
(Fig. 3)
tPZL 3003
177 "
178 "
179 "
180 "
181 "
182 "
183 "
184-
4.5V OUT
OUT 4.5V
"
"
4.5V OUT "
" "
"
"
"
" "
" OUT 4.5V "
"
"
4.5V OUT
OUT 4.5V
4.5V OUT
" OE to 2Q " " "
" OE to 3Q " " " " OE to 4Q " " "
" OE to 5Q " " " " OE to 6Q " " "
" OE to 7Q " " "
" OE to 8Q " " "
" " " "
" " " " " " " "
" " " " " " " "
" " " "
" " " "
(Fig. 3)
191 Same tests, terminal conditions and limits as specified above for tPLZ.
tTHL 3004 (Fig. 3)
tTLH 3004
192
193
194
195
196
197
198
199
200-
GN0 "
" "
"
" "
"
OUT IN
IN OUT
OUT IN
IN OUT
GN0 "
" "
"
" "
"
4.5V "
" "
"
" "
"
OUT IN
IN OUT
OUT IN
IN OUT
4.5V 1Q " 2Q " 3Q " 4Q " 5Q " 6Q " 7Q " 8Q
2 12 2 " " " " " " " " " " " " " " " " " " " " "
16 2 " " " " " " " " " " " " " "
12 ns
" "
" " " "
" "
" " " "
" "
(Fig. 3)
208 Same tests, terminal conditions and limits as specified above for tTHL.
11 Input pins not designated shall be "high" level logic or "low" level logic, or may be left open provided they do not influence the outcome of the measurement. Output pins not designated shall be tied to the loads or left open provided they do not influence the outcome of the measurement. Exceptions are as follows:
a. VIC(pos) tests, the GN0 terminal shall be open and the minimum limit of 0.4V applies only where test equipment limitations do not allow for the GN0 pin to be open during test.
b. VIC(neg) tests, the VCC terminal shall be open. c. ICC tests, the output terminal shall be open.
21 |
See 4.4.1c. |
|
31 |
Tests shall be performed in sequence, attributes data only. |
|
41 |
H > 2.5V; L < 2.5V; A = 3.7V; B = 0.4V, except for device 53; A = 2.4 V; B = 0.4 V. |
|
51 |
EN must be held at logic "1" while changing the address lines (A0, A1, A2) to select the next output bit. |
|
61 |
Apply 4.5 V 4.5 V |
|
0 V momentary |
||
pulse prior to each test. |
||
71 |
Three-state output conditions are required. For IOZL, set output to high state. For IOZH, set output to low state. VIL = VIL (max) and VIH = VIH (min), as required. |
Set input pins to |
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