MIL-M-38510-654 Microcircuits, Digital, High Speed, Cmos Latches, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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Test

8ymbol

Conditions 1/ TC = +125°C

unless otherwise specified

Device type

VCC

Limits

Unit

Min

Max

8hort circuit output current

IO81   2/

VO  = GND

VI  = GND or VCC

01-02

2.0 V

-2

-50

mA

03-06

-60

IO82   2/

01-02

4.5 V

-15

-150

03-06

-165

IO83   2/

01-02

6.0 V

-25

-180

03-06

-210

IO84

01-02

4.0 V

-10

-120

03-06,

53

-135

IO85   2/

53

5.5 V

-25

-210

Quiescent supply current

ICC

VI  = 6.0 V or GND

01

6.0 V

10

µA

02-06

20

ICC

VI  = 5.5 V or GND

53

5.5 V

20

ICCZ

VI  = 6.0 V

03-06

6.0 V

10

VI  = 5.5 V

53

5.5 V

Additional quiescent supply current

per input pin

(one unit load)

ICC�

3/

VIL  = 0.8 V

VIH  = 2.4 V, IO = 0

Pin under test at 2.4 V,

other pins at GND, 0.8 V, or VCC

53

5.5 V

3.0

µA

Power dissipation

capacitance

CPD  2/ 4/

TC = 25°C

01

46

pF

02

33

03

51

53

53

04-06

50

Three-state output

leakage current low

IOZL   5/

VOUT  = GND OC = VIH

03-06

6.0 V

-2.0

µA

53

5.5 V

Three-state output leakage current high

IOZH   5/

VOUT  = VCC

OC = VIH

03-06

6.0 V

+2.0

µA

53

5.5 V

Input capacitance

CIN

TC = 25°C

All

10

pF

Three-state output

capacitance

CO

03-06,

53

20

Propagation delay time, data to outputs

tPHL1, tPLH1

6/ 7/

CL  = 50 pF ± 10%

01

4.5 V

3

30

ns

02

5

43

03

6

35

04

6

39

05,06

4

41

53

6

41

Propagation delay time, enable or clock

to outputs

tPHL2, tPLH2

6/ 7/

01

4

34

02

7

47

03,53

6

41

04

6

41

05

4

41

06

4

41

Propagation delay time, A to outputs

tPHL3, tPLH3

6/, 7/

02

5

50