MIL-M-38510-653 Microcircuits, Digital, High Speed, Cmos Flip-Flops, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part or identifying number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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TABLE lll. Group A inspection - Continued.

11 Pins not designated may be high level logic, low level logic, or open. Exceptions are as follows:

a. VlC(pos) tests, the GND terminal shall be open. For test equipment that does not allow GND pin to be open during test, a minimum limit of O.4 V applies. b. VlC(neg) tests, the VCC terminal shall be open.

c. llC tests, the output terminals shall be open.

21	Apply one clock pulse prior to test as follows: 6.O V	or	6.O V	as appropriate.
	O.O V		O.O V

31	Apply one clock pulse prior to test as follows: 4.O V	or	4.O V	as appropriate.
	O.O V		O.O V

41 See 4.4.1c.

51 A = 3.7 V, B = O.4 V for all device types (except 52 where A = 2.4 V); H > 2.5 V, L < 2.5 V.

61 Only a summary of attributes data is required.

71 Apply input test parameters such that tsu, thold, trem, and tw values are not greater than the recommended operating minimums (see 1.4).

Preset outputs to required state if necessary prior to test.

81 See 4.4.1d.

91 The fMAX, minimum limit specified, is the frequency of the clock input. The data input is fMAX12

1O1 Apply one clock pulse prior to test as follows: 4.5 V or 4.5 V as appropriate.

O.O V O.O V

111 Three-state output conditions are required.