MIL-M-38510-653 Microcircuits, Digital, High Speed, Cmos Flip-Flops, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part or identifying number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-385101653B

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 11 TC = +125°C unless otherwise specified	Device type	VCC	Limits		Unit
Test	Symbol	Conditions 11 TC = +125°C unless otherwise specified	Device type	VCC	Min	Max
Propagation delay time, low to high level, CLK to Q	tPLH1	CL = 50 pF ± 10% 71 81	02,04 05,52	4.5 V	5	41	ns
			01-03		5	40
			06		6	47
			07		5	42
			08		4	41
Propagation delay time, high to low level, CLK to Q	tPHL1		02,04 05,52		5	41
			01-03		5	40
			06		6	47
			07		5	42
			08		4	41
Propagation delay time, low to high level, CLK or PRE to Q or Q	tPLH2		01,05		6	43
			02		5	54
			03		6	51
			04		6	54
			08		4	43
			52		5	47
Propagation delay time, high to low level, CLK or PRE to Q or Q	tPHL2		01,05		6	43
			02		5	54
			03		6	51
			04		6	54
			06		5	41
			07		5	42
			08		4	43
			52		5	47
Enable time to high or low level	tPZH or tPZL		06		5	35
Disable time to high or low level	tPHZ or tPLZ		06		5	35
Transition time, low to high level or high to low level	tTLH or tTHL		01-05 07,08,52		3	20
Transition time, low to high level or high to low level	tTLH or tTHL		06		2	16

11 Complete terminal conditions shall be as specified in table III.

21 Guaranteed but not tested.

31 Total supply current = ICC + ICC�.

41 IOZL sets internal D flip-flops to high state.

IOZH sets internal D flip-flops to low state.

51 Power dissipation capacitance (CPD) per flip-flop.

61 See the formula for determining maximum frequencies shown in table IA.

71 Tested at VCC = 4.5 V at +125°C for sample testing and VCC = 4.5 V and +25°C for screening.

Guaranteed at other VCC voltages and temperatures. See tables IA and IB (as appropriate) and the

exception in 4.4.1d.

81 For propagation and transition delay times at VCC = 2.0 V, increase limit by a factor of 5.

For propagation and transition delay times at VCC = 6.0 V, decrease limit by a factor of 0.85.