MIL-M-38510/2060
NOTES:
1. R1 = 4.7n ±5%. All bit outputs shall have separate identical loads.
2. All Addresses inputs shall be either high, low, or open.
3. R2 = 1 kn ±5%.
4. Burn-in circuit may be used to perform this test . All Address inputs shall be either high, low, or open.
5. For device type 03, the circuitry within the dashed lines is not present.
FIGURE 7. Freeze-out test bias configuration.
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