MIL-M-38510-2 Microcircuits, Digital, Ttl, Flip-Flops, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, TTL, bistable logic microcircuits. Three product assurance classes and a choice of case outlines/lead finish are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/2G

TABLE I. Electrical performance characteristics.

Test	Symbol	conditions 9/	Device Type	Limits		Units
Test	Symbol	conditions 9/	Device Type	Min	Max	Units
High-level output voltage	VOH	Vcc=4.5 V IOH = -400 µA	All	2.4	--	Volts
Low-level output voltage	VOL	Vcc = 4.5 V, IOL=16 mA	All		0.4	Volts
Input clamp voltage	VIc	Vcc = 4.5 V, IIc = -12 mA Tc = 25°c	All		-1.5	Volts
Low-level input current	IIL1	Vcc = 5.5 V VIN = 0.4 V 1/	01, 02, 03, 04, 05, 06	-0.7	-1.6	mA
Low-level input current	IIL1	Vcc = 5.5 V VIN = 0.4 V 1/	07	-0.5	-1.6	mA
Low-level input current	IIL2	Vcc = 5.5 V VIN = 0.4 V 2/	01, 02, 03, 04, 05	-1.4	-3.2	mA
Low-level input current	IIL2	Vcc = 5.5 V VIN = 0.4 V 2/	07	-1.0	-3.2	mA
Low-level input current	IIL3	Vcc = 5.5 V VIN = 0.4 V 6/	01, 02, 03, 04	-0.7	-3.2	mA
High-level input current	IIH1	Vcc = 5.5 V VIN = 2.4 V 5/	All		40	µA
High-level input current	IIH2	Vcc = 5.5 V VIN = 5.5 V 5/	All		100	µA
High-level input current	IIH3	Vcc = 5.5 V VIN = 2.4 V 3/	All 11/		80	µA
High-level input current	IIH4	Vcc = 5.5 V VIN = 5.5 V 3/ 7/	All		200	µA
High-level input current	IIH5	Vcc = 5.5 V VIN = 2.4 V 7/ 8/	01, 02, 03, 04, 05, 07	-50	-850 120	µA µA
High-level input current	IIH6	Vcc = 5.5 V VIN = 5.5 V 8/	05, 07		300	µA
Short-circuit output current	IOS	Vcc = 5.5 V VIN = 0 4/	All	-20	-57	mA
Supply current per device	Icc	Vcc = 5.5 V VIN = 5 V	01		20	mA
			02, 03, 04		40
			05, 06, 07		30
Maximum clock frequency 10/	fMAX	Vcc = 5 V cL = 50 pF minimum RL = 390n ± 5%	01, 02, 03 04, 05, 07	10		MHz
Maximum clock frequency 10/	fMAX		06	15		MHz
Propagation delay to high logic level (clear or preset to output)	tPLH		01, 02, 03, 04, 05	5	39	ns
			06	5	62
			07	5	31
Propagation delay to low logic level (clear or preset to output)	tPHL		01, 02, 03, 04, 05	5	50	ns
			06	5	62
			07	5	39
Propagation delay to high logic level (clock to output)	tPLH		06	5	62	ns
			01, 02, 03, 04, 05	5	39
			07	5	31
Propagation delay to low logic level (clock to output)	tPHL		06	5	62	ns
			01, 02, 03, 04, 05	5	50
			07	5	39

1/ Input condition - J or K for device types 01, 02, 03, 04, 06, and preset or D for device types 05 and 07, and clock, clear or preset for device type 06.

2/ Input condition - clock for device types 01, 02, 03 and 04, and clear or clock for device types 05 and 07.

3/ Input condition - clear or preset for device types 01, 02, 03, 04, 05, 06 and 07 and clock for device types 05 and 07.

4/ No more than one output should be shorted at a time.

5/ Input condition - J or K for device types 01, 02, 03, 04, 06, and D for device types 05 and 07, and clock for device type 06.

6/ Input condition - clear or preset for device types 01, 02, 03 and 04.

7/ Input condition - clock for device types 01, 02, 03 and 04.