MIL-M-38510-757 Microcircuits, Digital, Advanced Cmos, Buffer Gates, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, advanced CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance RHA are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/757C

4.2.1 Percent defective allowable (PDA).

a. The PDA for class S devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the exact number of devices submitted to each separate burn-in.

b. Static burn-in I and II failures shall be cumulative for determining the PDA.

c. The PDA for class B devices shall be in accordance with MIL-PRF-38535 for static burn-in. Dynamic burn-in is not required.

d. Those devices whose measured characteristics, after burn-in, exceed the specified delta () limits or electrical parameter limits specified in table I, subgroup 1, are defective and shall be removed from the lot. The verified number of failed devices times 100 divided by the total number of devices in the lot initially submitted to burn-in shall

be used to determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified

PDA.

4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535.

4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with

MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5).

4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows:

a. Tests shall be performed in accordance with table II herein.

b. O/V and O/I (latch-up) tests and VGBL/H (ground bounce) tests shall be measured only for initial qualification and

after process or design changes which may affect the performance of the device. Latch-up test shall be considered

destructive. Test all applicable pins on 5 devices with no failures.

c. CIN, COUT, and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN and COUT shall be measured between the designated terminal and GND at a frequency of

1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein.

For CIN, COUT, and CPD, test all applicable pins on five devices with zero failures.

d. Subgroups 9 and 11 shall be measured only for initial qualification and after process or design changes which may affect dynamic performance.

e. Subgroups 7 and 8 tests shall be sufficient to verify the truth table.

4.4.2 Group B inspection. Group B inspection shall be in accordance with table II of MIL-PRF-38535.