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MIL-M-38510-507 Microcircuits, Memory, Digital, CMOS Ultraviolet Erasable Programmable Array Logic, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS, erasable programmable array logic microcircuits which employ an EPROM cell as the programming element. Two product assurance classes B and S and a choice of case outlines and lead finishes are provided and are reflected in the complete part or identifying number PIN. For this product, the requirements of MIL-M-38510 have been

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MIL-M-38510/507B


TABLE III.  Operating modes.  1/

Pin Identification

Feature

Mode

CPI0

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

IO0

IO3

IO6

IO1 IO2

IO4 IO5

IO7 IO8

IO9

Main Array Product

Program

PP


Table V


Table VI

PP

Data In

Inhibit

PP

HP

High Z

Verify 2/

PP

LP

Data out

OE

Product

Terms

Program

PP


Table V

HP

HP

HP

PP

PP

Data In

Inhibit

PP

HP

HP

HP

PP

HP

High Z

Verify

PP

HP

HP

HP

PP

LP

Data out

SyncSet

Async 3/ Reset

TopTest

BotTest

Program

PP


Table V

HP

HP

HP

HP

PP

Data

In

Data

In

Data

In


LP

Data

In

Inhibit

PP

HP

HP

HP

HP

HP

Z

Z

Z

Z

Z

Verify

PP

HP

HP

HP

HP

LP

Data

Out

Data

Out

Data

Out


Driven

Data

Out

Archi-

tecture

Bits

Program

PP

HP

HP

HP

HP

HP

HP

LP


Table

VII

PP

PP

Data In

Inhibit

PP

HP

HP

HP

HP

HP

HP

LP

PP

HP

High Z

Verify

PP

HP

HP

HP

HP

HP

HP

LP

PP

LP

Data out

Security

Bit

Program

PP

LP

PP

LP

LP

LP

LP

LP

LP

LP

LP

PP

LP

LP

LP

LP

LP

Verify

LP

LP

Data

Out

PP

LP

LP

LP

LP

LP

LP

LP

LP

Driven Outputs

PAL Mode

Operatn

Normal

CP/I

I

I

I

I

I

I

I

I

I

I

I

I/O

Phantom

NA

I

NA

NA

NA

PP

I

NA

NA

I

I

NA

Output

TopTest

I

I

I

I

I

I

I

I

PP

I

I

I

NA

Out

BotTest

I

I

I

I

I

I

I

I

I

PP

I

I

Out

NA

RPreld

4/

NA

NA

NA

NA

NA

NA

PP

NA

NA

NA

LP

Data In

Phantom

Array

P Terms

Program

PP

LP

LP

Table

VIII

LP

PP

Table

VI

PP

Data In

Inhibit

PP

LP

LP

LP

PP

HP

High Z

Verify

PP

LP

LP

LP

PP

LP

Data Out

Phantom

OE

P Terms

Program

PP

LP

LP

Table

VIII

LP

PP

HP

HP

HP

PP

PP

Data In

Inhibit

PP

LP

LP

LP

PP

HP

HP

HP

PP

HP

High Z

Verify

PP

LP

LP

LP

PP

HP

HP

HP

PP

LP

Data Out


1/     Voltage legend:


LP = Low level input programming voltage (VILP). HP = High level input programming voltage (VIHP). PP = Program voltage (VPP).

Z = High impedance.


2/     It is necessary to toggle  OE  (I11) high during all address transitions while in the program verify/blank check mode.


3/     Data In and Data Out for programming Synchronous Set, Asynchronous Reset, Top Test and Bottom

Test is programmed and verified on the following pins: I/O0 = Bottom Test

I/O3 = Synchronous Set

I/O6 = Asynchronous Reset

I/O9 = Top Test


4/     The preload clock on CP/I0  loads the Registers on a low going high transition.


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