MIL-M-38510/507B
4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test
circuit shall be maintained under document control by the device manufacturer's Technology Review Board
(TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883.
c. The devices selected for testing shall be programmed with a minimum of 50 percent of the total number of cells programmed. After completion of all testing, the devices shall be erased and verified (except devices submitted for group D testing).
4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535 and as follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. The devices selected for testing shall be programmed with a minimum of 50 percent of the total number of cells programmed. After completion of all testing, the devices shall be erased and verified.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows:
4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional current and positive when flowing into the referenced terminal.
4.6 Programming procedure. The programming specifications on figure 5, figure 6, in table III, table IV, table V, table VI, table VII, table VIII, and the following procedures shall be used for programming the device:
a. Initially and after each erasure, all cells, with the exception of the security bit, are in the "0" state. A "1" indicates that an unprogrammed location is to be programmed and a "0" indicates that an unprogrammed location is to remain unprogrammed. All locations to be programmed are addressed as row and column locations. Table V through table VIII provide the specific address for each addressed location to be programmed.
b. The programming flow chart on figure 6 describes the sequence of operations for programming the Normal and Phantom arrays, the Normal and Phantom Output Enable product terms, the Set and Preset product terms, the Top Test product term, the Bottom Test product term, and the Architecture bits. The
sequencing and timing of the signals is shown on figure 5a. All setup, hold, and delay times must be met, and the sequence of operations should be strictly followed. Proper sequencing of all power and supervoltages is essential for reliable programming of the device.
c. After all locations are programmed, a verify of all words is required as shown on figure 5. When performing this verify only operation, eliminate the program portion of the cycle but maintain the setup and hold timing relative to the verify pulse. Under no circumstances should the verify signal be held low and the addresses toggled as it violates address setup and hold times. The overprogram pulse in step 10 of
figure 6 is a variable, "4" times the initial value when programming the Normal, Phantom, Top Test, Bottom Test and Output Enable product terms and "8" times the initial value when programming the Architecture bits.
d. The security cell is programmed per figure 5b with a single 50 ms pulse on I11. A supervoltage on I3 is used to verify the security cell after VPP has been removed from I0. Data in is represented as a supervoltage on I2 and verified as a TTL signal output on the same pin. A "0" on I2 indicates that the security bit has been programmed, and a "1" indicates that the security has not been programmed.
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