MIL-M-385101289A
TABLE I. Electrical performance characteristics - Continued.
Test |
Symbol |
Conditions 11 21 31 |
Device |
Limits |
Unit |
|
Min |
Max |
|||||
Chip select to end of write |
tELWH |
See table III and figure 5 |
01 |
35 |
ns |
|
02 |
30 |
ns |
||||
03 |
45 |
ns |
||||
04 |
50 |
ns |
||||
Address valid to end of write |
tAVWH |
01 |
35 |
ns |
||
02 |
30 |
ns |
||||
03 |
45 |
ns |
||||
04 |
50 |
ns |
||||
Address setup time |
tAVWL |
All |
0 |
ns |
||
Write pulse width |
tWLWH |
03 |
25 |
ns |
||
04 |
40 |
ns |
||||
01 |
20 |
ns |
||||
02 |
30 |
ns |
||||
Write recovery time |
tWHAX |
01 |
0 |
ns |
||
02,04 |
5 |
ns |
||||
03 |
10 |
ns |
||||
Data valid to end of write |
tDVWH |
01,02,04 |
20 |
ns |
||
03 |
25 |
ns |
||||
Data hold time |
tWHDX |
01,03 |
10 |
ns |
||
02,04 |
0 |
ns |
||||
Write enable to output in high Z 71, 51 |
tWLQZ |
01,04 |
0 |
20 |
ns |
|
02 |
0 |
10 |
ns |
|||
03 |
0 |
25 |
ns |
|||
Output active from end of write 71, 51 |
tWHQX |
All |
0 |
ns |
11 Output levels are tested in static state and are specified over voltage range of VCC.
21 Unless otherwise specified, the dynamic load shall be in accordance with figure 5 (load A).
31 Complete terminal conditions are as specified in table III.
41 Duration not to exceed 1 second.
51 Not tested.
61 Chip deselected for a finite time that is less than 55 ns prior to selection. (If the deselect time is 0 ns, the chip is by definition selected and access occurs according to Read Cycle No. 1.)
71 Transition is measured ± 500 mV from steady state voltage using figure 5 (load B).
4.4 Technology Conformance Inspection (TCI). Technology conformance inspection shall be in accordance with
MIL-PRF-38535 and as specified herein.
4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows:
a. Electrical test requirements shall be in accordance with table II herein. b. Subgroups 5 and 6 shall be omitted.
c. Subgroups 4 (Cin, Co measurement) shall be measured only for initial qualification and after process or design changes which may affect input and output capacitance. Capacitance shall be measured between the designated terminal and VSS at a frequency of 1 MHz and a signal amplitude not to exceed 50 mV rms. Perform Cin and Co parameter measurements to table I limits.
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