1.3 Absolute maximum ratings.
MIL-M-38510/289A
Voltage on any pin with respect to ground 2/ .................. -0.5 V dc to +7.0 V Storage temperature range ............................................ -65°C to +150°C Power dissipation (PD) ................................................. 1.0 mW
Lead temperature (soldering, 5 seconds) ....................... +270°C
Maximum junction temperature (TJ) 3/ ........................... +150°C Thermal resistance, junction-to-case ( θ JC) ..................
Cases V, Y and 3 (See MIL-STD-1835) Case X..................................................................... 55°C/W 4/
Maximum dc output current............................................. 20 mA
1.4 Recommended operating conditions.
Supply voltage range (VCC-VSS) ...................................... 4.5 V dc to 5.5 V dc
High level input voltage (VIH) (all inputs).......................... 2.0 V dc to 6.0 V dc (device 01, 02)
High level input voltage (VIH) (all inputs).......................... 2.0 V dc to VCC (device 03, 04)
Low level input voltage (VIL) (all inputs)........................... -3.0 V dc to +0.8 V dc
Operating case temperature (TC ).................................... -55°C to +125°C
Operating Condition |
DeviceType 01 |
Device Type 02 |
Device Type 03 |
Device Type 04 |
||||||||
Min |
Max |
Units |
Min |
Max |
Units |
Min |
Max |
Units |
Min |
Max |
Units |
|
Read Cycle Time (tAVAV) |
35 |
ns |
35 |
ns |
55 |
ns |
55 |
ns |
||||
Address access time (tAVQV) |
35 |
ns |
35 |
ns |
55 |
ns |
55 |
ns |
||||
Chip select access time (tELQV) |
35 |
ns |
35 |
ns |
55 |
ns |
65 8/ |
ns |
||||
Output hold time from address change (tAVQX) |
5 |
ns |
0 |
ns |
5 |
ns |
5 |
ns |
||||
Chip select to output in low Z (tELQL) 5/ 6/ |
5 |
ns |
10 |
ns |
5 |
ns |
10 |
ns |
||||
Chip deselect to output in high Z (tEHQZ) 5/ 6/ |
0 |
30 |
ns |
0 |
20 |
ns |
0 |
30 |
ns |
0 |
20 |
ns |
Chip select to power up time (tELPU) |
0 |
ns |
0 |
ns |
0 |
ns |
0 |
ns |
||||
Chip deselect to power down time (tEHPD) |
20 |
ns |
30 |
ns |
20 |
ns |
30 |
ns |
||||
Write cycle time (tAVAV) |
35 |
ns |
35 |
ns |
55 |
ns |
55 |
ns |
||||
Pulse width, chip select to end of write (tELWH) 7/ |
35 |
ns |
30 |
ns |
45 |
ns |
50 |
ns |
||||
Address valid to end of write (tAVWH) |
35 |
ns |
30 |
ns |
45 |
ns |
50 |
ns |
||||
Pulse width, write (tWLWH) |
20 |
ns |
30 |
ns |
25 |
ns |
40 |
ns |
||||
Data valid to end of write (tDVWH) |
20 |
ns |
20 |
ns |
25 |
ns |
20 |
ns |
||||
Address set up to write start (tAVWL) |
0 |
ns |
0 |
ns |
0 |
ns |
0 |
ns |
||||
Write recovery time (tWHAX) |
0 |
ns |
5 |
ns |
10 |
ns |
5 |
ns |
||||
Data hold from write end (tWHDX) |
10 |
ns |
0 |
ns |
10 |
ns |
0 |
ns |
||||
Write enabled to output in high Z (tWLQZ) 6/ |
0 |
20 |
ns |
0 |
10 |
ns |
0 |
25 |
ns |
0 |
20 |
ns |
Output active from end of write (tWHQX) 6/ 7/ |
0 |
ns |
0 |
ns |
0 |
ns |
0 |
ns |
||||
2/ Under absolute maximum ratings, the voltage values are with respect to the most negative supply voltage, VSS. Throughout the remainder of this specification, the voltage values are with respect to VSS.
3/ Maximum junction temperature (TJ) may be increased to 175°C during the burn in and steady state life test.
4/ When a thermal resistance value is included in MIL-STD-1835, it will
supersede the value stated herein.
5/ At any given temperature and voltage condition, tELQL maximum is less than tEHQZ minimum both for a given device and from device to device.
6/ Tansition is measured ± 500 mV from steady state voltage with specified loading.
7/ The internal write time of the memory is defined by the overlap of CS low and WE low. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
8/ Chip deselected less than 55 ns prior to selection.
2
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