MIL-M-38510-289 Microcircuits, Digital, Cmos 4096 Bit Static Random Access Memory Ram Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, CMOS static, 4096-bit random access memories. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/289A

TABLE I. Electrical performance characteristics.

Test	Symbol	Conditions 1/ 2/ 3/	Device	Limits		Unit
Test	Symbol	Conditions 1/ 2/ 3/	Device	Min	Max	Unit
Low level input leakage current (all input pins)	IIL	VCC = 5.5 V VIN = GND	All		-10	µA
High level input leakage current (all input pins)	IIH	VCC = 5.5 V VIN = 5.5 V	All		10	µA
Output leakage current	ILO	CS = VIH, VCC = 5.5 V VOUT = GND to 5.5 V	All		±50	µA
Power supply current	ICC	VCC = 5.5 V CS = VIL, outputs open	01,02		110	mA
Power supply current	ICC	VCC = 5.5 V CS = VIL, outputs open	03,04		140	mA
Standby current	ISB	VCC = 4.5 V to 5.5 V CS = VIH	01,02		10	mA
			03		25	mA
			04		30	mA
Output low voltage	VOL	IOL = 12.0 mA VIL = 0.8 V VIH = 2.0 V VCC = 4.5 V	01,03		0.4	V
Output low voltage	VOL	IOL = 8.0 mA	02,04		0.4	V
Output high voltage	VOH	VIL = 0.8 V VIH = 2.0 V VCC = 4.5 V IOH = - 4.0 mA	All	2.4		V
Output short circuit current 4/, 5/	IOS	VCC = 5.5 V, VOUT = GND	All		-350	mA
Input capacitance	CIN	VIN = 0 V, f = 1 MHz TC = 25qC	All		5	pF
Output capacitance	C0	VIN = 0 V, f = 1 MHz TC = 25qC	All		7	pF
Peak power on 5/	IPO	VCC = 4.5 V, CS = 2.4 V	All		10	mA
Read cycle time 2/	tAVAV	See table III and figure 5	01,02	35		ns
Read cycle time 2/	tAVAV		03,04	55		ns
Address access time	tAVQV		01,02		35	ns
Address access time	tAVQV		03,04		55	ns
Chip select access time 3/	tELQV		01,02		35	ns
			03		55	ns
			04 6/		65	ns
Chip select to output in low Z 5/ 7/	tELQX		01,03	5		ns
Chip select to output in low Z 5/ 7/	tELQX		02,04	10		ns
Chip deselect to output in high Z 5/ 7/	tEHQZ		01,03	0	30	ns
Chip deselect to output in high Z 5/ 7/	tEHQZ		02,04	0	20	ns
Output hold from address change	tAVQX		01,03,04	5		ns
Output hold from address change	tAVQX		02	0		ns
Chip select to power up time 5/	tELPU		All	0		ns
Chip deselect to power down time 5/	tEHPD		01,03		20	ns
Chip deselect to power down time 5/	tEHPD		02,04		30	ns
Write cycle time	tAVAV		01,02	35		ns
Write cycle time	tAVAV		03,04	55		ns

See footnotes at end of table.