MIL-M-38510/220
NOTES:
1. Clock input pulse characteristics for tPLH, tPHL (clock to output), Vgen = 3 V, t0 = t1 = 7 ns, tP(clock) = 20 ns, PRR = 1
MHz. When testing fMAX the clock input characteristics are Vgen = 3 V, t1 = t0 = 3 ns, tP(clock) = 10 ns, f = 36 MHz for
subgroup 9 and f = 30 MHz for subgroups 10 and 11. All J and K inputs are at 2.4 V.
2. J = (J1A · J1B) + (J2A · J2B) and K = (K1A · K1B) + (K2A · K2B).
3. All diodes are 1N3064, or equivalent.
4. CL = 50 pF ±5% (including jig and probe capacitance).
5. RL = 280 n ±5%.
6. J and K input characteristics for tPHL and tPLH are Vgen = 3 V, rise and fall times 10 ns maximum, and PW = 20 ns.
See table III for which tsetup to use.
7. For test 84, 85, 86, and 87 (high low temperature) the tsetup value shown above should be increased from 10 and 13 ns to 15 and 20 ns respectively.
FIGURE 13. Synchronous switching test circuit for device type 05.
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