TABLE III. Group A inspection for device type 08 - Continued.
Terminal conditions 17/
Subgroup |
Symbol |
MIL- STD-883 method |
Case E, F |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
Meas. terminal |
Test limits |
||
Test No. |
Data B Input |
Output QB |
Output QA |
Count Down |
Count Up |
Output QC |
Output QD |
GND |
Data D Input |
Data C Input |
Load |
Carry Output |
Borrow Output |
Clear Input |
Data A Input |
vCC |
Min |
Max |
Unit |
||||
10 TC =125°C |
14/ FMAX 14/ FMAX tPHL7 tPLH8 tPHL8 tPHL9 tPLH9 tPHL10 tPLH10 tPLH11 " " " tPHL11 " " " |
Fig 9A Fig 9A Fig 9 Fig 9 Fig 9 Fig 9A " " " " " " " " " " " |
134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 |
GND " " " GND GND 2.4 v 2.4 v GND GND 2.4 v GND |
OUT OUT |
OUT " " " " OUT OUT |
2.4 v 4/ GND GND GND 2.4 v 2.4 v 10/ 11/ 2.4 v 2.4 v 2.4 v 2.4 v 16/ 16/ 16/ 16/ |
4/ 2.4 v GND GND GND 8/ 9/ 2.4 v 2.4 v 15/ 15/ 15/ 15/ 2.4 v 2.4 v 2.4 v 2.4 v |
OUT OUT |
OUT OUT |
GND " " " " " " " " " " " " " " " " |
2.4 v 2.4 v GND GND GND GND GND GND 2.4 v GND GND GND |
GND " " " GND GND GND 2.4 v GND 2.4 v GND GND |
2.4 v 2.4 v 5/ 6/ 7/ 8/ 9/ 2.4 v 2.4 v 15/ 15/ 15/ 15/ 16/ 16/ 16/ 16/ |
OUT OUT |
OUT OUT |
GND GND 5/ GND GND 8/ GND 9/ 10/ 11/ GND " " " " " " " |
2.4 v 6/ 7/ GND " " " GND 2.4 v 2.4 v 2.4 v GND GND GND 2.4 v |
5.0 v " " " " " " " " " " " " " " " " |
QA QA QA QA QA Carry Carry Borrow Borrow QA QB QC QD QD QC QB QA |
20 20 3 " " " " " " " " " " " " " " |
57 66 62 39 45 39 42 63 63 63 63 71 71 71 71 |
MHz MHz ns " " " " " " " " " " " " " " |
11 |
Same tests, terminal conditions, and limits as subgroup 10, except TC = -55°C. |
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1/ Output voltages shall be either:
(a) H = 2.4 volts minimum and L = 0.4 volt maximum when using a high speed checker double comparator, or
(b) H �1.5 volts and L <1.5 volts when using a high speed checker single comparator.
2/ Only a summary of attributes data is required.
3/ A >2.0 v, B <0.8 v. Input voltages shown are the maximum for vIL and the minimum for vIH.
4/ See figure 9A. Apply waveform E for tests 117 and 134, and waveform H for tests 118 and 135.
5/ See figure 9, waveforms A, B, C, and D. Load AIN, then apply waveform A and observe the drop in QA output.
6/ See figure 9, waveforms B, C, and D. Load AIN, and observe tPLH of waveform D at output QA.
7/ Repeat steps as in note 6. Observe the pulse delay of the drop in QA when the load pulse is applied.
8/ See figures 9 and 9A, waveforms A, B, C, E, F, and G. First use clear pulse, then load pulse, then one count up pulse. Also see figure 9A, note 4.
9/ See note 5, add one more count up pulse for tPLH9 as shown on figure 10A, waveforms F and G.
10/ See figures 9 and 9A. First clear pulse, then one count down pulse.
11/ See note 7. Clear pulse first, figure 9 waveforms A, B, and C, add one more count down pulse for tPLH10 as shown on figure 9A, waveforms J and K.
12/ See figures 9 and 9A. First a clear pulse, then one count up pulse for QA. On next three tests enter count up pulses to appropriate count to
check QB, QC, and QD.
13/ See figure 9A waveforms H and J. On next three tests enter count down pulse, waveform H and observe tPHL11, waveform J on outputs QC, QB, and QA.
14/ FMAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency.
15/ Load pulse before count up input, then 4.5 v.
16/ Load pulse before count down input, then 4.5 v.
17/ Terminal conditions (pins not designated may be H � 2.0 v, or L ≤ 0.8 v, or open).
18/ The limits shall be: -0.5 mA minimum, -1.3 mA maximum for circuit C, and -0.7 mA minimum, -1.6 mA maximum for all other circuits.
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