MIL-M-38510-13 Microcircuits, Digital, Bipolar, Ttl, Counters Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, TTL, binary and decade counters. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/13G

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions -55°C ≤ TC ≤ +125°C unless otherwise specified	Device type	Limits		Unit
Test	Symbol	Conditions -55°C ≤ TC ≤ +125°C unless otherwise specified	Device type	Min	Max	Unit
Low-level input current at data inputs	IIL6	VCC = 5.5 V, VIN = 0.4 V	03, 04, 05, 06	-0.4	-1.3	mA
Low-level input current at data inputs	IIL6	VCC = 5.5 V, VIN = 0.4 V	08, 09	-0.5	-1.6	mA
Low-level input current at clear, enable, and load	IIL7	VCC = 5.5 V, VIN = 0.4 V	03, 04, 05 06, 08, 09	-0.5	-1.6	mA
Low-level input current at count enable T	IIL8	VCC = 5.5 V, VIN = 0.4 V	03, 04, 05 06	-1.0	-3.2	mA
Short-circuit supply current	IOS	VCC = 5.5 V 1/	01, 02, 03 04, 05, 06 07	-20	-57	mA
Short-circuit supply current	IOS	VCC = 5.5 V 1/	08, 09	-20	-65	mA
Supply current	ICC	VCC = 5.5 V, VIN = 4.5 V	01, 02, 07		44	mA
Supply current	ICC	VCC = 5.5 V, VIN = 4.5 V	08, 09		89	mA
High-level supply current	ICCH	VCC = 5.5 V 2/	03, 04, 05, 06		85	mA
Low-level supply current	ICCL	VCC = 5.5 V 3/	03, 04 05, 06		91	mA
Maximum frequency of input count pulses	FMAX	VCC = 5.0 V CL = 50 pF ±10% RL = 390 ±5%	01, 02, 07	10		MHz
Maximum input clock frequency	FMAX		03, 04, 05, 06, 08, 09	20		MHz
Propagation delay time to logical H level from input count pulse to output D	tPLH1		01, 07	20	115	ns
Propagation delay time to logical L level from input count pulse to output D	tPHL1		01, 07	20	115	ns
Propagation delay time to logical H level from input count pulse to output D	tPLH2		02	20	135	ns
Propagation delay time to logical L level from input count pulse to output D	tPHL2		02	20	135	ns
Propagation delay time, low-to-high-level carry output from clock	tPLH3		03, 04 05, 06	3	58	ns
Propagation delay time, high-to-low-level carry output from clock	tPHL3		03, 04 05, 06	3	58	ns
Propagation delay time, low-to-high-level Q output from clock	tPLH4		03, 04 05, 06	3	36	ns
Propagation delay time, high-to-low-level Q output from clock	tPHL4		03, 04 05, 06	3	38	ns

See footnotes at end of table.