TABLE III. Group A inspection for device type 05 - Continued.
Terminal conditions 21
11 Normal clock pulse: (VIL < 0.8 V, VIH > 2.0 V).
21 Terminal conditions (pins not designated may be H > 2.0 V, or L < 0.8 V, or open).
31 Output voltages shall be either:
(a) H = 2.4 volts minimum and L = 0.4 volt maximum when using a high speed checker double comparator, or
(b) H > 1.5 volts and L < 1.5 volts when using a high speed checker single comparator.
41 Only a summary of attributes data is required.
51 A > 2.0 V, B < 0.8 V. Input voltages shown are the maximum for VIL and the minimum for VIH.
61 FMAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency.
71 Apply 1 clock pulse prior to input pulses.
81 Momentarily ground, then apply 4.5 V.
91 Minimum limit for circuit C shall be -0.5 mA.
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