MIL-M-38510-657 Microcircuits, Digital, High-Speed Cmos, Buffer Gates, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-385101657A

TABLE III.  Group A inspection - Continued.

11    Output pins not designated may be "high" level logic, "low" level logic, or open.  Input pins not designated may be

"high" level logic or "low" level logic.  Exceptions are as follows:

a.        VIC(pos) tests, the GND terminal shall be open.  A minimum limit of 0.4 V applies to tests being performed on equipment not capable of opening the "GND" pin during test.

b.    VIC(neg) tests, the VCC  terminal shall be open. c.    ICC  tests, the output terminal shall be open.

21    See 4.4.1c.

31    Decrement input in 50 mV steps beginning 100 mV above the maximum limit specified until the output changes from GND to VDD.  The input voltage where this transition occurs is VT-.

IN             - - - - -- - - - - - - - - - - - - - - - - -    VDD

- - - - - - - - - - - - - -    VT-

- - - -    GND

- - - -    VDD

OUT                                       - - - - - - - - -    GND

41    Increment input in 50 mV steps beginning 100 mV below the minimum limit specified until the output changes from VDD  to GND.  The input voltage where this transition occurs is VT+.

51    VH  = (VT+) - (VT-).  See table III for VH  limits.

61    A = 3.7 V B = 0.4 V

71    Output shall be:  High z 1.5 V;  Low s 1.5 V;  IOUT  = 20 µA.

81    A = 2.4 V B = 0.4 V

91    Three-state output conditions are required.  For IOZL, set output to high state.  For IOZH, set output to low state.  Set input pins to VIL  = VIL (max) and VIH  = VIH  (min), as required.

91