MIL-M-38510-657 Microcircuits, Digital, High-Speed Cmos, Buffer Gates, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

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MIL-M-38510/657A

TABLE I.  Electrical performance characteristics - Continued.

1/    Complete terminal conditions and limits shall be as specified in table III.

2/    Guaranteed but not tested.

3/    IOZL  set buffer output to high state.  IOZH  set buffer output to low state.

4/    Total supply current ICC  + ICC�.

5/    Power dissipation capacitance (CPD) typically per inverter (device types 01, 02, 51, 52) or per buffer

(device types 03-11, 53-55, 60, 61).

6/    Tested at VCC = 4.5 V at +125°C for sample testing and VCC  = 4.5 V at +25°C for screening.  Guaranteed at other

VCC  voltages and temperatures.  See table IA and exception in 4.4.1d.

7/    For propagation and transition delay times at VCC  = 2.0 V, increase limit by a factor of 5.  For propagation and transition delay times at VCC  = 6.0 V, decrease limit by a factor of 0.85.

TABLE IA.  Calculated dynamic figures at -55°C/25°C ambient temperature.

Normalized numbers

(+125°C equals 1)

NOTE:   The 2.0 V and 6.0 V numbers are derived from their 4.5 V integer value (rounding off according 5/4).

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