MIL-M-38510-133 Microcircuits, Linear, 10-Bit Digital-To-Analog Converter, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, 10-bit binary digital-to-analog converters containing deposited thin film resistor networks. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3

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Test

Symbol

Conditions  1/

-55°C ≤ TA  ≤ +125°C

unless otherwise specified

Device

types

Limits

Unit

Min

Max

Gain error drift

dAE2/dt

Change in VFS  from -55°C to +125°C

01

-0.006

+0.006

%/°C

Power supply sensitivity at full-scale from VCC:      TTL

CMOS

+PSS1

All digital inputs at VCC;

VCC  = +5 ±0.5 V, TA = 25°C    4/

01

-0.01

+0.01

LSB/%PS

VCC  = +5±0.5 V, -55°C < TA < 125°C

-0.02

+0.02

+PSS2

VCC  = +15±1.5 V, TA = 25°C    4/

-0.01

+0.01

VCC  = +15±1.5 V,

-55°C < TA  < 125°C

-0.02

+0.02

Power supply sensitivity at full-scale from VEE:  CMOS

TTL

-PSS1

VEE  = -15±1.5 V, TA = 25°C    4/

01

-0.025

+0.025

LSB/%PS

VEE  = -15±1.5 V, -55°C < TA < 125°C

-0.05

+0.05

-PSS2

VEE  = -12±1.2 V, VCC  = +5.0 V,

TA  = 25°C    4/

-0.025

+0.025

VEE  = -12±1.2 V, VCC  = +5.0 V,

-55°C < TA  < 125°C

-0.05

+0.05

Linearity error (end point)

LE

All combinations of bits 1 to 4, bits 5 to 10 are turned off.  Measure VO relative to REF DAC output.  Record the code words for the worst case positive bit error; and for the worst case negative bit error.    5/

01

-0.5

+0.5

LSB

Turn on bits 5 to 10, one bit at a time, and measure relative to REF DAC output.  Bits 1 to 4 are turned off.  Record the measured bit error sign.     5/

-0.5

+0.5

Linearity error (end point)

LE

(All codes test)  See table III

01

-0.5

+0.5

LSB

Major carry errors

MCE1 - MCE10

The difference between adjacent codes at all major transitions (i.e. from 01111111 to 10000000)   4/

01

-1.0

+1.0

LSB

Output current settling

time (to �  LSB) 0 V to FS

tSLH

VCC  = +5 V.  All inputs switched simultaneously.  Measure the time to settle to within � LSB of the final value. TA  = 25°C.

(see figures 3 and 4)

01

500

ns

Output current settling

time (to �  LSB) FS to 0 V

tSLH

VCC  = +5 V.  All inputs switched simultaneously.  Measure the time to settle to within � LSB of the final value. TA  = 25°C.

(see figures 3 and 4)

01

500

ns

Noise

NO

VCC = +5.0 V; VEE = -15 V, 0 V,

All digital inputs at +2.2 V,

see figure 5. TA  = 25°C, BW =100 kHz,        5/   6/

01

160

µV rms