MIL-M-38510-125 Microcircuits, Linear, Sample And Hold Circuits, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, sample and hold circuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4

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Test

Symbol

Conditions

-55°C ≤ TA ≤ +125°C

±VCC = ±15 V, see figure 3 and 3.5

unless otherwise specified

Device type

Limits

Unit

Min

Max

Input offset voltage   1/

VIO

±VCC = ±5 V to ±15 V, TA = +25°C

01,02

-3

3

mV

±VCC = ±5 V to ±15 V,

-55°C ≤ TA ≤ +125°C

-5

5

Input offset voltage

temperature sensitivity

�VIO /

�T

TA = -55°C to +25°C

01,02

-20

20

µV/°C

TA = +25°C to +125°C

-20

20

Input bias current     1/

IIB

±VCC = ±5 V to ±15 V, TA = +25°C

01,02

-1

25

nA

±VCC = ±5 V to ±15 V,

-55°C ≤ TA ≤ +125°C

-25

75

Input impedance   2/

ZI

TA = +25°C

01,02

2

Gn

-55°C ≤ TA ≤ +125°C

1

Gain error

AE

VIN = -11.5 V to +11.5 V, RL = 10 kn, TA = +25°C

01,02

-.005

+.005

%

VIN = -11.5 V to +11.5 V, RL = 10 kn,

-55°C ≤ TA ≤ +125°C

-0.02

+0.02

VIN = -10 V to +10 V, RL = 2 kn, TA = +25°C

02

-.005

+.005

VIN = -10 V to +10 V, RL = 2 kn,

-55°C ≤ TA ≤ +125°C

-0.02

+0.02

VCC = ±5 V, RL = 10 kn,

VIN = -2 V to +2 V, TA = +25°C

01,02

-0.02

+0.02

VCC = ±5 V, VIN = -2 V to +2 V,

RL = 10 kn,  -55°C ≤ TA ≤ +125°C

-0.04

+0.04

Input offset voltage

adjustment

VIO

(ADJ+)

VIN = 0 V, VOFFSET ADJ at +VCC

01,02

+6

mV

VIO

(ADJ-)

VIN = 0 V,

VOFFSET ADJ at 1 kn from +VCC,

20 kn from 0 V

-6