MIL-M-38510-650 Microcircuits, Digital, High-Speed Cmos, Nand Gates, Monolithic Silicon, Positive LogicThis specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete Part or Identifying Number PIN. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535 see 6.3.

Pages 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33

MIL-M-38510/650C

TABLE I. Electrical performance characteristics - Continued.

Test	Symbol	Conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified	Device types	VCC	Limits		Unit
Test	Symbol		Device types	VCC	Min	Max	Unit
Propagation delay times	tPHL, tPLH 4/ 5/	CL = 50 pF +10 percent	01	4.5 V	3	21	ns
			02	4.5 V	3	23
			03	4.5 V	3	26
			04	4.5 V	6	41
			05	4.5 V	4	29
Transition delay times	tTHL, tTLH 4/ 5/	CL = 50 pF +10 percent	01	4.5 V	3	20	ns
			02	4.5 V	3	20
			03	4.5 V	3	20
			04	4.5 V	3	20
			05	4.5 V	3	20

1/ Complete terminal conditions shall be as specified in table III.

2/ Guaranteed but not tested.

3/ Power dissipation capacitance (CPD) per gate.

4/ Tested at VCC = 4.5 V at +125°C for sample testing and VCC = 4.5 V at +25°C for screening. Guaranteed at other VCC

voltages and temperatures, see table IA and exception in 4.4.1d.

5/ For propagation and transition delay times at VCC = 2.0 V, increase limit by a factor of 5.

For propagation and transition delay times at VCC = 6.0 V, decrease limit by a factor of 0.85.

TABLE IA. Calculated dynamic figures at -55°C/+25°C case temperature.

Normalized numbers

(125°C equals 1)

NOTE: The 2.0 V and 6.0 V numbers are derived from their 4.5 V integer value.

Rounding off according 5/4.