MIL-M-38510/61C
|
||
Device types 01 and 02 |
||
ASYNCHRONOUS |
|
SYNCHRONOUS |
|
* This is an unstable condition, when X = Don't care
clear (CLR) and preset (P/S) inputs C = C E + CC
return to their low level (inactive state) *A clock H is a clock transition
these states will not be maintained. transition from a low to a high state.
Preset (P/S) and clear (CLR) override clock (CC) and clock enable (CE) inputs. Each flip-flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip-flop, the clock enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock. The outputs states of the flip-flop change on the positive transition of the clock.
Device type 03 SYNCHRONOUS
|
||||
|
|
|
|
X = Don't care |
|
|
|
|
*A clock H is a clock transition |
|
|
|
|
transition from a low to a high state. |
|
||||
Clocking is common to all six flip-flops. Data transfer is accomplished on positive going transition of the clock.
Device type 04
ASYNCHRONOUS SYNCHRONOUS
* This is an unstable condition, when Output states change on positive
clear (CLR) and preset (P/S) inputs transition of clock for J- K input
return to their low level (inactive state) conditions present.
these states will not be maintained.
Preset (P/S) and clear (CLR) override the clock. The output states of the flip-flop change on the positive transition of
the clock.
FIGURE 2. Truth tables.
12
Source: https://assist.dla.mil -- Downloaded:
Check the source to verify that this is the current version before use.
For Parts Inquires call Parts Hangar, Inc (727) 493-0744
© Copyright 2015 Integrated Publishing, Inc.
A Service Disabled Veteran Owned Small Business