MIL-M-38510-61 Microcircuits, Digital, Ecl, Flip-Flops, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, ECL, logic gating microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.3.

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Test

Symbol

Conditions 

-55°C = TC = +125°C   1/

Device

types

Limits

Unit

Min

Max

Maximum clock

  frequency

FMAX

VEEL = -3.2 V, VCC = +2.0 V CL = 5 pF (output under test) Load = 100ν to GND

01

105

MHz

02

200

03

115

04

105

Transition time,

  low to high level

tTLH      

VEEL = -3.2 V, VCC = +2.0 V,

RL

= 50ν, CL = 5 pF (output under test)

2

Load = 100ν to GND (outputs not 

           under test)

01

1.0

4.9

ns

02

1.0

3.6

03

1.0

4.7

04

1.0

5.3

Transition time,

  high to low level

tTHL

01

1.0

4.9

ns

02

1.0

3.6

03

1.0

4.7

04

1.0

5.3

Propagation delay time,

  low to high level (clear or

  preset to output

tPLH1

01

1.1

4.9

ns

02

1.0

3.9

04

1.0

5.9

Propagation delay time,

  high to low level (clear or

  preset to output

tPHL1     

VEE = -3.2 V, VCC = +2.0 V,

RL

= 50ν, CL = 5 pF (output under test)

2

Load = 100ν to GND (outputs not 

           under test)

01

1.1

4.9

ns

02

1.0

3.9

04

1.0

5.9

Propagation delay time,

  low to high level (clock

  to output

tPLH2

01

1.4

5.0

ns

02

1.2

3.9

03

1.3

5.3

04

1.0

5.3

Propagation delay time,

  high to low level (clock

  to output

tPHL2

01

1.4

5.0

ns

02

1.2

3.9

03

1.3

5.3

04

1.0

5.3