MIL-M-38510-207 Microcircuit, Digital, 256-Bit, Schottky, Bipolar, Programmable Read-Only Memory Prom, Monolithic SiliconThis specification covers the detail requirements for monolithic silicon, PROM microcircuits which employ thin film nichrome NiCr resistors, tungsten W, titanium tungsten TiW, or zapped vertical emitter ZVE as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead material and finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, see 6.4.

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MIL-M-38510/207E

4.11  Programming procedure for circuit H.   The programming characteristics in table IVH and the following procedures shall apply for programming the device:

a.  Connect the device in the electrical configuration for programming.  The waveforms on figure 5E and the programming characteristics in table IVH shall apply for programming to these procedures.

b.  Terminate all device outputs with a 10 kn resistor to VCC.  The 10 kn is the pullup resistor for open collector devices.

c.   Address the PROM with the binary address of the selected word to be programmed.  Raise VCC to VCCP. d.  After a tD delay (10 us), apply VOPF output to be programmed.  Program one output at a time.

Note leading edge rise time restrictions.

e.  After a tD delay (10 us), pulse  CE  input to logic "0" for a duration of tP.

f.  After a tD delay (10 us), remove the VOPF pulse from the programmed output.  Note that the PROM is supplied with fuses generating a low-level logic output.  Programming a fuse will cause the output to go to a high-level logic in the verify mode.

g.  Repeat 4.11d through 4.11f to program other bits at the same address.

h.  To verify programming of all bits at the same address, after tD delay lower VCC to VCCVL and apply a logic low level to the  CE X input.  All programmed outputs should remain in the same logic high state.

i.    After tD delay, repeat steps 4.11c through 4.11h to program and verify all other address locations.

j.    After tD delay, raise VCC to VCCVH and verify all memory locations by applying a logic low level to

CE  and cycling through all device addresses.

k.   For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject.

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